PIC18F45K80-I/PT Microchip Technology, PIC18F45K80-I/PT Datasheet - Page 128

• Manufacturer Part Number: PIC18F45K80-I/PT
• Description: MCU PIC 32KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K80-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F45K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F66K80 FAMILY
6.4
While the program memory can be addressed in only
one way, through the program counter, information in
the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The addressing modes are:
• Inherent
• Literal
• Direct
• Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1 ). For details on
this mode’s operation, see
Addressing with Literal Offset”
6.4.1
Many PIC18 control instructions do not need any
argument at all. They either perform an operation that
globally affects the device or they operate implicitly on
one register. This addressing mode is known as Inherent
Addressing. Examples of this mode include SLEEP ,
RESET and DAW .
Other instructions work in a similar way, but require an
additional explicit argument in the opcode. This method
is known as the Literal Addressing mode because the
instructions require some literal value as an argument.
Examples of this include ADDLW and MOVLW , which
respectively, add or move a literal value to the W
register. Other examples include CALL and GOTO ,
which include a 20-bit program memory address.
6.4.2
Direct Addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies the instruction’s data
source as either a register address in one of the banks
DS39977C-page 128
Note:
Data Addressing Modes
The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. For
Section 6.6 “Data Memory and the
Extended Instruction Set”
INHERENT AND LITERAL
ADDRESSING
DIRECT ADDRESSING
more
Section 6.6.1 “Indexed
.
information, see
.
Preliminary
of data RAM (see
Register File”
Section 6.3.2 “Access Bank”
The Access RAM bit, ‘a’, determines how the address
is interpreted. When ‘a’ is ‘ 1 ’, the contents of the BSR
(
the address to determine the complete 12-bit address
of the register. When ‘a’ is ‘ 0 ’, the address is interpreted
as being a register in the Access Bank. Addressing that
uses the Access RAM is sometimes also known as
Direct Forced Addressing mode.
A few instructions, such as MOVFF , include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit, ‘d’. When ‘d’ is ‘ 1 ’, the results are
stored back in the source register, overwriting its origi-
nal contents. When ‘d’ is ‘ 0 ’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction,
either the target register being operated on or the W
register.
6.4.3
Indirect Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special Function Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures such as
tables and arrays in data memory.
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code using
loops, such as the example of clearing an entire RAM
bank in
Indexed
operations for program memory in data memory.
EXAMPLE 6-5:
Section 6.3.1 “Bank Select Register”
NEXT
CONTINUE
Example
LFSR
CLRF
BTFSS
BRA
Addressing
INDIRECT ADDRESSING
) or a location in the Access Bank (see
6-5. It also enables users to perform
FSR0, 100h ;
POSTINC0
FSR0H, 1
NEXT
Section 6.3.3 “General Purpose
HOW TO CLEAR RAM
(BANK 1) USING INDIRECT
ADDRESSING
 2011 Microchip Technology Inc.
and
).
other
; Clear INDF
; register then
; inc pointer
; All done with
; Bank1?
; NO, clear next
; YES, continue
Stack
) are used with
Pointer