PIC18F45K80-I/PT Microchip Technology, PIC18F45K80-I/PT Datasheet - Page 136

• Manufacturer Part Number: PIC18F45K80-I/PT
• Description: MCU PIC 32KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K80-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F45K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F66K80 FAMILY
FIGURE 7-2:
7.2
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
7.2.1
The EECON1 register
register for memory accesses. The EECON2 register,
not a physical register, is used exclusively in the
memory
EECON2 will read all ‘ 0 ’s.
The EEPGD control bit determines if the access is a
program or data EEPROM memory access. When
clear, any subsequent operations operate on the data
EEPROM memory. When set, any subsequent
operations operate on the program memory.
The CFGS control bit determines if the access is to the
Configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
operate on Configuration registers regardless of
EEPGD (see
CPU”
determined by EEPGD.
DS39977C-page 136
). When clear, memory selection access is
Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by
Control Registers
TBLPTRU
write
EECON1 AND EECON2 REGISTERS
Section 28.0 “Special Features of the
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 7.5 “Writing to Flash Program
and
Table Pointer
TBLPTRH
TABLE WRITE OPERATION
erase
(Register
(1)
sequences.
TBLPTRL
7-1) is the control
Program Memory
(TBLPTR)
Reading
Preliminary
Instruction:
Memory”.
Holding Registers
Program Memory
The FREE bit, when set, allows a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, allows a write operation. On
power-up, the WREN bit is clear. The WRERR bit is set
in hardware when the WR bit is set and cleared when
the internal programming timer expires and the write
operation is complete.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the write operation.
TBLWT
Note:
Note:
*
During normal operation, the WRERR is
read as ‘ 1 ’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
The EEIF interrupt flag bit (PIR4<6>) is
set when the write is complete. It must be
cleared in software.
 2011 Microchip Technology Inc.
Table Latch (8-bit)
TABLAT