PIC18F45K80-I/PT Microchip Technology, PIC18F45K80-I/PT Datasheet - Page 235

• Manufacturer Part Number: PIC18F45K80-I/PT
• Description: MCU PIC 32KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K80-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F45K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.5.2
The Timer3 gate source can be selected from one of
four different sources. Source selection is controlled by
the T3GSS<1:0> bits (T3GCON<1:0>). The polarity for
each available source is also selectable and is
controlled by the T3GPOL bit (T3GCON<6>).
TABLE 16-2:
16.5.2.1
The T3G pin is one source for Timer3 gate control. It can
be used to supply an external source to the Timerx gate
circuitry.
16.5.2.2
The TMR4 register will increment until it matches the
value in the PR4 register. On the very next increment
cycle, TMR4 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be gener-
ated and internally supplied to the Timerx gate circuitry.
The pulse will remain high for one instruction cycle and
will return back to a low state until the next match.
Depending on T3GPOL, Timerx increments differently
when TMR4 matches PR4. When T3GPOL = 1 , Timer3
increments for a single instruction cycle following a
FIGURE 16-3:
 2011 Microchip Technology Inc.
T3GSS<1:0>
TMR3GE
T3GPOL
T3GVAL
T3G_IN
T3GTM
Timer3
00
01
10
11
T3CKI
TIMER3 GATE SOURCE
SELECTION
T3G Pin Gate Operation
Timer4 Match Gate Operation
Timerx Gate Pin
TMR4 to Match PR4
(TMR4 increments to match PR4)
Comparator 1 Output
(comparator logic high output)
Comparator 2 Output
(comparator logic high output)
TIMER3 GATE SOURCES
N
TIMER3 GATE TOGGLE MODE
Timer3 Gate Source
N + 1 N + 2 N + 3
Preliminary
PIC18F66K80 FAMILY
TMR4 match with PR4. When T3GPOL = 0 , Timer3
increments continuously, except for the cycle following
the match, when the gate signal goes from low-to-high.
16.5.2.3
The output of Comparator 1 can be internally supplied
to the Timer3 gate circuitry. After setting up
Comparator 1 with the CM1CON register, Timer3 will
increment depending on the transitions of the
CMP1OUT (CMSTAT<6>) bit.
16.5.2.4
The output of Comparator 2 can be internally supplied
to the Timer3 gate circuitry. After setting up
Comparator 2 with the CM2CON register, Timer3 will
increment depending on the transitions of the
CMP2OUT (CMSTAT<7>) bit.
16.5.3
When Timer3 Gate Toggle mode is enabled, it is
possible to measure the full cycle length of a Timer3
gate signal, as opposed to the duration of a single level
pulse.
The Timer3 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. (For timing details, see
The T3GVAL bit will indicate when the Toggled mode is
active and the timer is counting.
Timer3 Gate Toggle mode is enabled by setting the
T3GTM bit (T3GCON<5>). When the T3GTM bit is
cleared, the flip-flop is cleared and held clear. This is
necessary in order to control which edge is measured.
N + 4
TIMER3 GATE TOGGLE MODE
Comparator 1 Output Gate
Operation
Comparator 2 Output Gate
Operation
N + 5 N + 6 N + 7
Figure
DS39977C-page 235
16-3.)
N + 8