PIC18F45K80-I/PT Microchip Technology, PIC18F45K80-I/PT Datasheet - Page 238

• Manufacturer Part Number: PIC18F45K80-I/PT
• Description: MCU PIC 32KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K80-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F45K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F66K80 FAMILY
16.6
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in the interrupt flag bit, TMR3IF.
Table 16-3
This interrupt can be enabled or disabled by setting or
clearing the TMR3IE bit.
module’s enable bit.
16.7
If the ECCP modules are configured to use Timer3 and
to generate a Special Event Trigger in Compare mode
(CCP3M<3:0> = 1011 ), this signal will reset Timer3.
The trigger from ECCP will also start an A/D conversion
if the A/D module is enabled (For more information, see
Section 20.3.4 “Special Event Trigger”
TABLE 16-3:
DS39977C-page 238
INTCON
PIR5
PIE5
PIR2
PIE2
TMR3H
TMR3L
T3GCON
T3CON
OSCCON2
PMD1
Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used by the Timer3 module.
Name
Timer3 Interrupt
Resetting Timer3 Using the ECCP
Special Event Trigger
gives each module’s flag bit.
Timer3 Register High Byte
Timer3 Register Low Byte
TMR3CS1
GIE/GIEH
TMR3GE
OSCFIF
OSCFIE
PSPMD
IRXIF
IRXIE
Bit 7
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
—
PEIE/GIEL
SOSCRUN
TMR3CS0
CTMUMD
Table 16-3
T3GPOL
WAKIF
WAKIE
Bit 6
—
—
displays each
.)
T3CKPS1
TMR0IE
ADCMD
T3GTM
ERRIF
ERRIE
Bit 5
—
—
—
Preliminary
SOSCDRV
T3CKPS0
TMR4MD
T3GSPM
TXB2IF
TX2BIE
INT0IE
Bit 4
—
—
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPR3H:CCPR3L register
pair effectively becomes a Period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
Special Event Trigger from an ECCP module, the write
will take precedence.
Note:
Note:
SOSCGO
TMR3MD
SOSCEN
T3DONE
T3GGO/
TXB1IE
TXB1IF
BCLIF
BCLIE
RBIE
Bit 3
The Special Event Triggers from the
ECCPx module will only clear the TMR3
register’s content, but not set the TMR3IF
interrupt flag bit (PIR2<1>).
The CCP and ECCP modules use Timers,
1 through 4, for some modes. The assign-
ment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRS register. For
more details, see
Register
TMR2MD
T3SYNC
T3GVAL
TMR0IF
TXB0IE
HLVDIF
HLVDIE
TXB0IF
Bit 2
19-2.
—
 2011 Microchip Technology Inc.
TMR1MD
T3GSS1
TMR3IE
MFIOFS
RXB1IE
TMR3IF
RXB1IF
INT0IF
RD16
Bit 1
Register 20-2
TMR3GIE
TMR3GIF
MFIOSEL
TMR3ON
TMR0MD
T3GSS0
RXB0IF
RXB0IE
Bit 0
RBIF
and