PIC18F45K80-I/PT Microchip Technology, PIC18F45K80-I/PT Datasheet - Page 361

• Manufacturer Part Number: PIC18F45K80-I/PT
• Description: MCU PIC 32KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K80-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F45K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.5
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTAx<7>). This mode differs from the
Synchronous Master mode in that the shift clock is sup-
plied externally at the CKx pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
22.5.1
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
If two words are written to the TXREGx and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
TABLE 22-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
 2011 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTA1
TXREG1
TXSTA1
BAUDCON1
SPBRGH1
SPBRG1
RCSTA2
TXREG2
TXSTA2
BAUDCON2
SPBRGH2
SPBRG2
PMD0
ODCON
Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used for synchronous slave transmission.
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in the TXREGx
register.
Flag bit, TXxIF, will not be set.
When the first word has been shifted out of TSR,
the TXREGx register will transfer the second word
to the TSR and flag bit, TXxIF, will now be set.
Name
EUSART Synchronous
Slave Mode
EUSART SYNCHRONOUS
SLAVE TRANSMISSION
EUSART1 Transmit Register
EUSART2 Transmit Register
EUSART1 Baud Rate Generator Register High Byte
EUSART1 Baud Rate Generator Register Low Byte
EUSART2 Baud Rate Generator Register High Byte
EUSART2 Baud Rate Generator Register Low Byte
GIE/GIEH
ABDOVF
ABDOVF
CCP5MD
SSPOD
PSPIE
PSPIP
PSPIF
CSRC
CSRC
SPEN
SPEN
Bit 7
—
—
—
PEIE/GIEL
CCP4MD
CCP5OD
RCIDL
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
RX9
TX9
TX9
—
—
—
CCP3MD
CCP4OD
TMR0IE
RXDTP
RXDTP
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
SREN
TXEN
TXEN
Bit 5
Preliminary
CCP2MD
CCP3OD
TXCKP
TXCKP
INT0IE
CREN
CREN
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
SYNC
SYNC
Bit 4
PIC18F66K80 FAMILY
e)
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
If enable bit, TXxIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Clear bits, CREN and SREN.
If interrupts are desired, set enable bit, TXxIE.
If 9-bit transmission is desired, set bit, TX9.
Enable the transmission by setting enable bit,
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Start transmission by loading data to the
TXREGx register.
If using interrupts, ensure that the GIE and PEIE
bits (INTCON<7:6>) are set.
CCP1MD
CCP2OD
CTMUIE
CTMUIP
CTMUIF
ADDEN
SENDB
ADDEN
SENDB
BRG16
BRG16
SSPIE
SSPIP
SSPIF
RBIE
Bit 3
UART2MD UART1MD
TMR1GIE
TMR1GIP
TMR1GIF
CCP1OD
TMR0IF
CCP2IE
CCP2IP
CCP2IF
BRGH
BRGH
FERR
FERR
Bit 2
—
—
TMR2IF
TMR2IE
TMR2IP
CCP1IE
CCP1IP
CCP1IF
INT0IF
OERR
OERR
U2OD
TRMT
TRMT
WUE
WUE
Bit 1
DS39977C-page 361
TMR1IF
TMR1IE
TMR1IP
SSPMD
ABDEN
ABDEN
U1OD
RX9D
RX9D
TX9D
TX9D
RBIF
Bit 0
—
—
—