PIC18F45K80-I/PT Microchip Technology, PIC18F45K80-I/PT Datasheet - Page 386

MCU PIC 32KB FLASH 44TQFP

PIC18F45K80-I/PT

Manufacturer Part Number
PIC18F45K80-I/PT
Description
MCU PIC 32KB FLASH 44TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of PIC18F45K80-I/PT

Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Number Of I /o
35
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP
Controller Family/series
PIC18
Ram Memory Size
4KB
Cpu Speed
16MIPS
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, USART
Processor Series
PIC18F45K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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PIC18F66K80 FAMILY
FIGURE 25-1:
25.2
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure
ence source rails. The voltage reference is derived
from the reference source; therefore, the CV
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in
25.3
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
DS39977C-page 386
25-1) keep CV
Section 31.0 “Electrical Characteristics”
Voltage Reference Accuracy/Error
Operation During Sleep
V
V
AV
CVREN
REF
REF
DD
REF
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
-
+
from approaching the refer-
CVRSS =
CVRSS =
CVRSS =
CVRSS =
0
1
32 Steps
REF
1
0
output
Preliminary
8R
.
R
R
R
R
R
R
R
clearing bit, CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RF5 pin by clearing
25.4
A device Reset disables the voltage reference by
bit, CVROE (CVRCON<6>).
25.5
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA0 pin if the
CVROE bit is set. Enabling the voltage reference out-
put onto RA0 when it is configured as a digital input will
increase current consumption. Connecting RA0 as a
digital output with CVRSS enabled will also increase
current consumption.
The RA0 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to V
Figure 25-2
Effects of a Reset
Connection Considerations
CVR<4:0>
shows an example buffering technique.
 2011 Microchip Technology Inc.
CV
REF
REF
.

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