PIC18F45K80-I/PT Microchip Technology, PIC18F45K80-I/PT Datasheet - Page 398

• Manufacturer Part Number: PIC18F45K80-I/PT
• Description: MCU PIC 32KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K80-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F45K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F66K80 FAMILY
REGISTER 27-1:
DS39977C-page 398
Mode 0
Mode 1
Mode 2
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3-1
bit 0
bit 4-0
Note 1:
This bit will clear when all transmissions are aborted.
bit 7
REQOP<2:0>: Request CAN Operation Mode bits
1xx = Request Configuration mode
011 = Request Listen Only mode
010 = Request Loopback mode
001 = Disabled/Sleep mode
000 = Request Normal mode
ABAT: Abort All Pending Transmissions bit
1 = Abort all pending transmissions (in all transmit buffers)
0 = Transmissions proceeding as normal
Mode 0:
WIN<2:0>: Window Address bits
These bits select which of the CAN buffers to switch into the Access Bank area. This allows access to the
buffer registers from any data memory bank. After a frame has caused an interrupt, the ICODE<3:0> bits
can be copied to the WIN<2:0> bits to select the correct buffer. See
111 = Receive Buffer 0
110 = Receive Buffer 0
101 = Receive Buffer 1
100 = Transmit Buffer 0
011 = Transmit Buffer 1
010 = Transmit Buffer 2
001 = Receive Buffer 0
000 = Receive Buffer 0
Mode 0:
Unimplemented: Read as ‘ 0 ’
Mode 1:
Unimplemented: Read as ‘ 0 ’
Mode 2:
FP<3:0>: FIFO Read Pointer bits
These bits point to the message buffer to be read.
0000 = Receive Message Buffer 0
0001 = Receive Message Buffer 1
0010 = Receive Message Buffer 2
0011 = Receive Message Buffer 3
0100 = Receive Message Buffer 4
0101 = Receive Message Buffer 5
0110 = Receive Message Buffer 6
0111 = Receive Message Buffer 7
1000:1111 Reserved
REQOP2
REQOP2
REQOP2
R/W-1
R/W-1
R/W-1
CANCON: CAN CONTROL REGISTER
REQOP1
REQOP1
REQOP1
R/W-0
R/W-0
R/W-0
S = Settable bit
W = Writable bit
‘1’ = Bit is set
REQOP0
REQOP0
REQOP0
R/W-0
R/W-0
R/W-0
Preliminary
R/S-0
ABAT
R/S-0
ABAT
R/S-0
ABAT
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
WIN2
FP3
R-0
U0
—
(1)
R/W-0
WIN1
Example 27-2
FP2
U-0
R-0
—
 2011 Microchip Technology Inc.
x = Bit is unknown
R/W-0
WIN0
FP1
U-0
R-0
for a code example.
—
FP0
U-0
U-0
R-0
—
—
bit 0