PIC18F45K80-I/PT Microchip Technology, PIC18F45K80-I/PT Datasheet - Page 445

• Manufacturer Part Number: PIC18F45K80-I/PT
• Description: MCU PIC 32KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K80-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F45K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.5.4
In Mode 1 and 2, any of six programmable transmit/
receive buffers may be programmed to automatically
respond to predefined RTR messages without user
firmware intervention. Automatic RTR handling is
enabled by setting the TX2EN bit in the BSEL0 register
and the RTREN bit in the BnCON register. After this
setup, when an RTR request is received, the TXREQ
bit is automatically set and the current buffer content is
automatically queued for transmission as a RTR
response. As with all transmit buffers, once the TXREQ
bit is set, buffer registers become read-only and any
writes to them will be ignored.
The
automatically handle RTR messages:
1.
2.
3.
4.
Normally, user firmware will keep buffer data registers
up to date. If firmware attempts to update the buffer
while an automatic RTR response is in the process of
transmission, all writes to buffers are ignored.
27.6
27.6.1
For the MCU to have write access to the message buf-
fer, the TXREQ bit must be clear, indicating that the
message buffer is clear of any pending message to be
transmitted. At a minimum, the SIDH, SIDL and DLC
registers must be loaded. If data bytes are present in
the message, the Data registers must also be loaded.
If the message is to use extended identifiers, the
EIDH:EIDL registers must also be loaded and the
EXIDE bit set.
To initiate message transmission, the TXREQ bit must
be set for each buffer to be transmitted. When TXREQ
is set, the TXABT, TXLARB and TXERR bits will be
cleared. To successfully complete the transmission,
there must be at least one node with matching baud
rate on the network.
 2011 Microchip Technology Inc.
Set buffer to Transmit mode by setting the
TXnEN bit to
At least one acceptance filter must be associ-
ated with this buffer and preloaded with the
expected RTR identifier.
Bit, RTREN in the BnCON register, must be set
to
Buffer must be preloaded with the data to be
sent as a RTR response.
following
‘
1
’
CAN Message Transmission
.
INITIATING TRANSMISSION
PROGRAMMABLE AUTO-RTR
BUFFERS
outlines
‘
1
’
in the BSEL0 register.
the
steps
required
Preliminary
to
PIC18F66K80 FAMILY
Setting the TXREQ bit does not initiate a message
transmission; it merely flags a message buffer as ready
for transmission. Transmission will start when the
device detects that the bus is available. The device will
then begin transmission of the highest priority message
that is ready.
When the transmission has completed successfully, the
TXREQ bit will be cleared, the TXBnIF bit will be set and
an interrupt will be generated if the TXBnIE bit is set.
If the message transmission fails, the TXREQ will remain
set, indicating that the message is still pending for trans-
mission and one of the following condition flags will be
set. If the message started to transmit but encountered
an error condition, the TXERR and the IRXIF bits will be
set and an interrupt will be generated. If the message lost
arbitration, the TXLARB bit will be set.
27.6.2
The MCU can request to abort a message by clearing
the TXREQ bit associated with the corresponding mes-
sage buffer (TXBnCON<3> or BnCON<3>). Setting the
ABAT bit (CANCON<4>) will request an abort of all
pending messages. If the message has not yet started
transmission, or if the message started but is interrupted
by loss of arbitration or an error, the abort will be pro-
cessed. The abort is indicated when the module sets the
TXABT bit for the corresponding buffer (TXBnCON<6>
or BnCON<6>). If the message has started to transmit,
it will attempt to transmit the current message fully. If the
current message is transmitted fully and is not lost to
arbitration or an error, the TXABT bit will not be set
because the message was transmitted successfully.
Likewise, if a message is being transmitted during an
abort request and the message is lost to arbitration or an
error, the message will not be retransmitted and the
TXABT bit will be set, indicating that the message was
successfully aborted.
Once an abort is requested by setting the ABAT or
TXABT bits, it cannot be cleared to cancel the abort
request. Only CAN module hardware or a POR
condition can clear it.
ABORTING TRANSMISSION
DS39977C-page 445