PIC18F45K80-I/PT Microchip Technology, PIC18F45K80-I/PT Datasheet - Page 455

MCU PIC 32KB FLASH 44TQFP

PIC18F45K80-I/PT

Manufacturer Part Number
PIC18F45K80-I/PT
Description
MCU PIC 32KB FLASH 44TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of PIC18F45K80-I/PT

Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Number Of I /o
35
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP
Controller Family/series
PIC18
Ram Memory Size
4KB
Cpu Speed
16MIPS
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, USART
Processor Series
PIC18F45K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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FIGURE 27-7:
27.11 Programming Time Segments
Some requirements for programming of the time
segments:
• Prop_Seg + Phase_Seg 1  Phase_Seg 2
• Phase_Seg 2  Sync Jump Width.
For example, assume that a 125 kHz CAN baud rate is
desired, using 20 MHz for F
a baud rate prescaler value of 04h gives a T
To obtain a Nominal Bit Rate of 125 kHz, the Nominal
Bit Time must be 8  s or 16 T
Using 1 T
and 7 T
point at 10 T
Phase Segment 2.
 2011 Microchip Technology Inc.
T
Q
Q
for Phase Segment 1 would place the sample
Q
for the Sync_Seg, 2 T
Q
Sync
after the transition. This leaves 6 T
SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2)
Segment
Prop
OSC
Q
.
. With a T
Q
for the Prop_Seg
OSC
Actual Bit Length
Q
of 500 ns.
of 50 ns,
Segment 1
Phase
Q
Preliminary
Nominal Bit Length
for
Sample Point
PIC18F66K80 FAMILY
By the rules above, the Sync Jump Width could be the
maximum of 4 T
only necessary when the clock generation of the
different nodes is inaccurate or unstable, such as using
ceramic resonators. Typically, an SJW of 1 is enough.
27.12 Oscillator Tolerance
As a rule of thumb, the bit timing requirements allow
ceramic resonators to be used in applications with
transmission rates of up to 125 Kbit/sec. For the full bus
speed range of the CAN protocol, a quartz oscillator is
required. Refer to ISO11898-1 for oscillator tolerance
requirements.
Segment 2
Phase
Q
. However, normally a large SJW is
DS39977C-page 455
 SJW

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