PIC18F45K80-I/PT Microchip Technology, PIC18F45K80-I/PT Datasheet - Page 458

• Manufacturer Part Number: PIC18F45K80-I/PT
• Description: MCU PIC 32KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K80-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F45K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

buffers to detect the source of interrupt.
PIC18F66K80 FAMILY
27.15.1
To simplify the interrupt handling process in user firm-
ware, the ECAN module encodes a special set of bits. In
Mode 0, these bits are ICODE<3:1> in the CANSTAT
register. In Mode 1 and 2, these bits are EICODE<4:0> in
the CANSTAT register. Interrupts are internally prioritized
such that the higher priority interrupts are assigned lower
values. Once the highest priority interrupt condition has
been cleared, the code for the next highest priority inter-
rupt that is pending (if any) will be reflected by the ICODE
bits (see
sources that have their associated interrupt enable bit set
will be reflected in the ICODE bits.
In Mode 2, when a receive message interrupt occurs,
the EICODE bits will always consist of ‘ 10000 ’. User
firmware may use FIFO Pointer bits to actually access
the next available buffer.
27.15.2
When the transmit interrupt is enabled, an interrupt will
be generated when the associated transmit buffer
becomes empty and is ready to be loaded with a new
message. In Mode 0, there are separate interrupt enable/
disable and flag bits for each of the three dedicated trans-
mit buffers. The TXBnIF bit will be set to indicate the
source of the interrupt. The interrupt is cleared by the
MCU, resetting the TXBnIF bit to a ‘ 0 ’. In Mode 1 and 2,
all transmit buffers share one interrupt enable/disable bit
and one flag bit. In Mode 1 and 2, TXBnIE in PIE5 and
TXBnIF in PIR5 indicate when a transmit buffer has com-
pleted transmission of its message. TXBnIF, TXBnIE and
TXBnIP in PIR5, PIE5 and IPR5, respectively, are not
used in Mode 1 and 2. Individual transmit buffer interrupts
can be enabled or disabled by setting or clearing TXBnIE
and B0IE register bits. When a shared interrupt occurs,
user firmware must poll the TXREQ bit of all transmit
27.15.3
When the receive interrupt is enabled, an interrupt will
be generated when a message has been successfully
received and loaded into the associated receive buffer.
This interrupt is activated immediately after receiving
the End-of-Frame (EOF) field.
In Mode 0, the RXBnIF bit is set to indicate the source
of the interrupt. The interrupt is cleared by the MCU,
resetting the RXBnIF bit to a ‘ 0 ’.
In Mode 1 and 2, all receive buffers share RXBnIE,
RXBnIF and RXBnIP in PIE5, PIR5 and IPR5, respec-
tively. Bits, RXBnIE, RXBnIF and RXBnIP, are not
used. Individual receive buffer interrupts can be con-
trolled by the TXBnIE and BIE0 registers. In Mode 1,
when a shared receive interrupt occurs, user firmware
must poll the RXFUL bit of each receive buffer to detect
the source of interrupt. In Mode 2, a receive interrupt
indicates that the new message is loaded into FIFO.
FIFO can be read by using FIFO Pointer bits, FP.
DS39977C-page 458
Table
INTERRUPT CODE BITS
TRANSMIT INTERRUPT
RECEIVE INTERRUPT
27-4). Note that only those interrupt
Preliminary
TABLE 27-4:
27.15.4
When an error occurs during transmission or reception
of a message, the message error flag, IRXIF, will be set
and if the IRXIE bit is set, an interrupt will be generated.
This is intended to be used to facilitate baud rate
determination when used in conjunction with Listen
Only mode.
27.15.5
When the PIC18F66K80 family devices are in Sleep
mode and the bus activity wake-up interrupt is enabled,
an interrupt will be generated and the WAKIF bit will be
set when activity is detected on the CAN bus. This
interrupt causes the PIC18F66K80 family devices to
exit Sleep mode. The interrupt is reset by the MCU,
clearing the WAKIF bit.
27.15.6
When the CAN module error interrupt (ERRIE in PIE5)
is enabled, an interrupt is generated if an overflow con-
dition occurs, or if the error state of the transmitter or
receiver has changed. The error flags in COMSTAT will
indicate one of the following conditions.
Legend:
ERR = ERRIF * ERRIE
TX0 = TXB0IF * TXB0IE
TX1 = TXB1IF * TXB1IE
TX2 = TXB2IF * TXB2IE
ICODE
<2:0>
000
001
010
011
100
101
110
111
Interrupt
Wake on
Interrupt
RXB1
RXB0
TXB2
TXB1
TXB0
None
Error
MESSAGE ERROR INTERRUPT
BUS ACTIVITY WAKE-UP
INTERRUPT
ERROR INTERRUPT
VALUES FOR ICODE<2:0>
ERR•WAK•TX0•TX1•TX2•RX0•RX1
ERR
ERR•TX0•TX1•TX2
ERR•TX0•TX1
ERR•TX0
ERR•TX0•TX1•TX2•RX0•RX1
ERR•TX0•TX1•TX2•RX0
ERR•TX0•TX1•TX2•RX0•RX1•WAK
 2011 Microchip Technology Inc.
Boolean Expression
RX1 = RXB1IF * RXB1IE
WAK = WAKIF * WAKIE
RX0 = RXB0IF * RXB0IE