PIC18F45K80-I/PT Microchip Technology, PIC18F45K80-I/PT Datasheet - Page 462

• Manufacturer Part Number: PIC18F45K80-I/PT
• Description: MCU PIC 32KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K80-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F45K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F66K80 FAMILY
TABLE 28-1:
DS39977C-page 462
3FFFFEh DEVID1
Legend:
Note 1:
30000Ch CONFIG7L
30000Dh CONFIG7H
3FFFFFh DEVID2
30000Ah CONFIG6L
30000Bh CONFIG6H
300000h CONFIG1L
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
300005h CONFIG3H MCLRE
300006h CONFIG4L DEBUG
300008h CONFIG5L
300009h CONFIG5H
File Name
2:
3:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Implemented only on the 64-pin devices (PIC18F6XK80).
See
Maintain as ‘ 0 ’ on 28-pin, 40-pin and 44-pin devices.
Register 28-13
(2)
(2)
CONFIGURATION BITS AND DEVICE IDs
DEV10
WRTD
DEV2
IESO
Bit 7
CPD
—
—
—
—
—
—
—
for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
BORPWR1 BORWPR0
WDTPS4
FCMEN
EBTRB
XINST
WRTB
DEV1
DEV9
Bit 6
CPB
—
—
—
—
—
WDTPS3
WRTC
DEV0
DEV8
Bit 5
—
—
—
—
—
—
—
—
—
Preliminary
SOSCSEL1 SOSCSEL0 INTOSCSEL
WDTPS2
PLLCFG
BBSIZ0
BORV1
REV4
DEV7
Bit 4
—
—
—
—
—
—
—
MSSPMSK T3CKMX
WDTPS1
FOSC3
BORV0
EBTR3
WRT3
REV3
DEV6
Bit 3
CP3
—
—
—
—
BOREN1
WDTPS0
FOSC2
EBTR2
WRT2
REV2
DEV5
Bit 2
CP2
—
—
—
—
(1,3)
T0CKMX
BOREN0 PWRTEN
WDTEN1 WDTEN0
FOSC1
EBTR1
WRT1
REV1
DEV4
Bit 1
 2011 Microchip Technology Inc.
CP1
—
—
—
—
—
(1)
STVREN
CANMX
RETEN
FOSC0
EBTR0
WRT0
REV0
DEV3
Bit 0
CP0
—
—
—
Unprogrammed
-1-1 11-1
00-0 1000
-111 1111
-111 1111
1--- 1qq1
1--1 ---1
---- 1111
11-- ----
---- 1111
111- ----
---- 1111
-1-- ----
xxxx xxxx
xxxx xxxx
Default/
Value