PIC18F45K80-I/PT Microchip Technology, PIC18F45K80-I/PT Datasheet - Page 483

• Manufacturer Part Number: PIC18F45K80-I/PT
• Description: MCU PIC 32KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K80-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F45K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

28.6
The user program memory is divided into four blocks.
One of these is a boot block of 1 or 2 Kbytes. The
remainder of the memory is divided into blocks on
binary boundaries.
FIGURE 28-6:
 2011 Microchip Technology Inc.
Note 1: Sizes of memory areas are not to scale.
000000h
01FFFFh
200000h
3FFFFFh
Program Verification and
Code Protection
2: Boot block size is determined by the BBSIZ0 bit (CONFIG4L<4>).
Unimplemented
Code Memory
Configuration
Read as ‘
and ID
Space
CODE-PROTECTED PROGRAM MEMORY FOR THE PIC18F66K80 FAMILY
0
’
Preliminary
Boot Block
BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0
Block 0
Block 1
Block 2
Block 3
2 kW
6 kW
8 kW
8 kW
8 kW
PIC18F66K80 FAMILY
PIC18FX6K80
Each of the blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPx)
• Write-Protect bit (WRTx)
• External Block Table Read bit (EBTRx)
Figure 28-6
48, 64, 96 and 128 Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in
Device/Memory Size
Boot Block Boot Block
Block 0
Block 1
Block 2
Block 3
7 kW
8 kW
8 kW
8 kW
shows the program memory organization for
Block 0
Block 1
Block 2
Block 3
2 kW
2 kW
4 kW
4 kW
4 kW
PIC18FX5K80
(1)
Boot Block 0000h
Block 0
Block 1
Block 2
Block 3
3 kW
4 kW
4 kW
4 kW
DS39977C-page 483
0800h
1000h
1FFFh
2000h
3FFFh
4000h
5FFFh
6000h
7FFFh
8000h
BFFFh
C000h
FFFFh
10000h
13FFFh
14000h
17FFFh
18000h
1BFFFh
1C000h
1FFFFh
Table
Address
28-4.