PIC18F45K80-I/PT Microchip Technology, PIC18F45K80-I/PT Datasheet - Page 621

• Manufacturer Part Number: PIC18F45K80-I/PT
• Description: MCU PIC 32KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K80-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F45K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SUBFSR ........................................................................... 533
SUBFWB........................................................................... 522
SUBLW ............................................................................. 523
SUBULNK ......................................................................... 533
SUBWF ............................................................................. 523
SUBWFB........................................................................... 524
SWAPF ............................................................................. 524
T
Table Pointer Operations (table) ....................................... 138
Table Reads/Table Writes ................................................ 109
TBLRD .............................................................................. 525
TBLWT .............................................................................. 526
Time-out in Various Situations (table) ................................. 86
Timer0 ............................................................................... 211
Timer1 ............................................................................... 215
Timer2 ............................................................................... 227
Timer3 ............................................................................... 229
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Associated Registers ................................................ 213
Operation .................................................................. 212
Overflow Interrupt ..................................................... 213
Prescaler................................................................... 213
Prescaler Assignment (PSA Bit) ............................... 213
Prescaler Select (T0PS2:T0PS0 Bits) ...................... 213
Reads and Writes in 16-Bit Mode ............................. 212
Source Edge Select (T0SE Bit)................................. 212
Source Select (T0CS Bit).......................................... 212
16-Bit Read/Write Mode............................................ 220
Associated Registers ................................................ 226
Clock Source Selection............................................. 218
Gate .......................................................................... 222
Interrupt..................................................................... 221
Operation .................................................................. 218
Oscillator ................................................................... 215
Oscillator, as Secondary Clock ................................... 58
Resetting, Using the ECCP Special
SOSC Oscillator........................................................ 220
TMR1H Register ....................................................... 215
TMR1L Register........................................................ 215
Associated Registers ................................................ 228
Interrupt..................................................................... 228
Operation .................................................................. 227
Output ....................................................................... 228
PR2 Register............................................................. 268
TMR2 to PR2 Match Interrupt ................................... 268
16-Bit Read/Write Mode............................................ 233
Associated Registers ................................................ 238
Gates ........................................................................ 234
Operation .................................................................. 232
Oscillator ................................................................... 229
Overflow Interrupt ............................................. 229, 238
SOSC Oscillator
Special Event Trigger (ECCP) .................................. 238
TMR3H Register ....................................................... 229
TMR3L Register........................................................ 229
Switching Assignment....................................... 213
Event Trigger .................................................... 222
Layout Considerations ...................................... 221
Use as a Clock Source ..................................... 221
Use as the Timer3 Clock Source ...................... 233
Preliminary
PIC18F66K80 FAMILY
Timer4 .............................................................................. 239
Timing Diagrams
Associated Registers................................................ 240
Interrupt .................................................................... 240
Operation.................................................................. 239
Output....................................................................... 240
Postscaler. See Postscaler, Timer4.
PR4 Register ............................................................ 239
Prescaler. See Prescaler, Timer4.
TMR4 Register ......................................................... 239
A/D Conversion ........................................................ 588
Asynchronous Reception.......................................... 353
Asynchronous Transmission .................................... 350
Asynchronous Transmission (Back-to-Back)............ 350
Automatic Baud Rate Calculation............................. 348
Auto-Wake-up Bit (WUE) During Normal
Auto-Wake-up Bit (WUE) During Sleep.................... 355
Baud Rate Generator with Clock Arbitration............. 325
BRG Overflow Sequence ......................................... 348
BRG Reset Due to SDA Arbitration During
Brown-out Reset (BOR)............................................ 574
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start Condition
Bus Collision During a Stop Condition (Case 1)....... 336
Bus Collision During a Stop Condition (Case 2)....... 336
Bus Collision During Start Condition
Bus Collision for Transmit and Acknowledge ........... 332
Capture/Compare/PWM (ECCP1, ECCP2).............. 577
CLKO and I/O ........................................................... 572
Clock/Instruction Cycle ............................................. 110
DSM Carrier High Synchronization (MDCHSYNC = 1,
DSM Carrier Low Synchronization
DSM Full Synchronization
DSM No Synchronization
DSM On-Off Keying (OOK) Synchronization............ 204
Enhanced PWM Output (Active-High) ...................... 278
Enhanced PWM Output (Active-Low) ....................... 279
EUSART Synchronous Transmission
EUSART/AUSART
Example SPI Master Mode (CKE = 0) ...................... 578
Example SPI Master Mode (CKE = 1) ...................... 579
Example SPI Slave Mode (CKE = 0) ........................ 580
Example SPI Slave Mode (CKE = 1) ........................ 581
External Clock .......................................................... 570
Fail-Safe Clock Monitor (FSCM)............................... 482
First Start Bit Timing ................................................. 326
Full-Bridge PWM Output........................................... 282
Operation.......................................................... 355
Start Condition.................................................. 334
Condition (Case 1)............................................ 335
Condition (Case 2)............................................ 335
(SCL = 0) .......................................................... 334
(SDA Only) ....................................................... 333
MDCLSYNC = 0) .............................................. 204
(MDCHSYNC = 0, MDCLSYNC = 1) ................ 205
(MDCHSYNC = 1, MDCLSYNC = 1) ................ 205
(MDCHSYNC = 0, MDCLSYNC = 0) ................ 204
(Master/Slave) .................................................. 586
Slave) ............................................................... 586
Synchronous
DS39977C-page 621
Receive
(Master/