IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 11

• Manufacturer Part Number: IDT82P5088BBG
• Description: IC LIU T1/E1/J1 OCTAL 256PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P5088BBG

• Includes: Integrated Clock Adapter
• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Power (watts): 2.57W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

Table-1 Pin Description (Continued)
Notes:
1. TCLKn missing: the state of TCLKn continues to be high level or low level over 70 clock cycles.
PIN DESCRIPTION
IDT82P5088
RD1/RDP1
RD2/RDP2
RD3/RDP3
RD4/RDP4
RD5/RDP5
RD6/RDP6
RD7/RDP7
RD8/RDP8
CV1/RDN1
CV2/RDN2
CV3/RDN3
CV4/RDN4
CV5/RDN5
CV6/RDN6
CV7/RDN7
CV8/RDN8
TD1/TDP1
TD2/TDP2
TD3/TDP3
TD4/TDP4
TD5/TDP5
TD6/TDP6
TD7/TDP7
TD8/TDP8
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
TCLK8
Name
TDN1
TDN2
TDN3
TDN4
TDN5
TDN6
TDN7
TDN8
Output
Output
Input
Input
Type
PBGA256
Pin No.
G2
G4
D2
C2
G3
D1
C1
B1
K3
K1
H2
H4
R2
R1
N2
M4
M2
N3
N1
M3
M1
M6
R5
N5
F2
F4
E2
E4
F1
F3
E1
E3
L3
L1
P3
P1
L5
T2
T1
P2
L4
T6
P6
T4
P4
T3
J3
J1
TDn: Transmit Data for Channel 1~8
In Single Rail Mode, the NRZ data to be transmitted is input on these pins. Data on TDn is sampled into the device on
the active edge of TCLKn. The active edge of TCLKn is selected by the TCLK_SEL bit (TCF0, 22H...). Data is encoded
by AMI, HDB3 or B8ZS line code rules before being transmitted to the line. In this mode, TDNn should be connected
to ground.
TDPn/TDNn: Positive/Negative Transmit Data for Channel 1~8
In Dual Rail Mode, the NRZ data to be transmitted is input on these pins. Data on TDPn/TDNn is sampled into the
device on the active edge of TCLKn. The active edge of the TCLKn is selected by the TCLK_SEL bit (TCF0, 22H...)
The line code in Dual Rail Mode is as follows:
TCLKn: Transmit Clock for Channel 1~8
These pins input 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode transmit clock. The transmit data on TDn orT-
DPn/TDNn is sampled into the device on the active edge of TCLKn. If TCLKn is missing
rupt is not masked, an interrupt will be generated.
RDn: Receive Data for Channel 1~8
In Single Rail Mode, the NRZ receive data is output on these pins. Data is decoded according to AMI, HDB3 or B8ZS
line code rules. The active level on RDn pin is selected by the RD_INV bit (RCF0, 28H...).
CVn: Code Violation for Channel 1~8
In Single Rail Mode, the BPV/CV errors in received data streams will be reported by driving pin CVn to high level for
a full clock cycle. The B8ZS/HDB3 line code violation can be indicated when the B8ZS/HDB3 decoder is enabled.
When AMI decoder is selected, the bipolar violation can be indicated.
RDPn/RDNn: Positive/Negative Receive Data for Channel 1~8
In Dual Rail Mode with Clock & Data Recovery (CDR), these pins output the NRZ data with the recovered clock. An
active level on RDPn indicates the receipt of a positive pulse on RTIPn/RRINGn while an active level on RDNn indi-
cates the receipt of a negative pulse on RTIPn/RRINGn. The active level on RDPn/RDNn is selected by the RD_INV
bit (RCF0, 28H...). When CDR is disabled, these pins directly output the raw RZ sliced data. The output data on RDn
and RDPn/RDNn is updated on the active edge of RCLKn.
RCLKn: Receive Clock for Channel 1~8
These pins output 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode receive clock. Under LOS conditions, if RAISE
bit (MAINT1, 2CH...) is ‘1’, RCLKn is derived from MCLK.
In clock recovery mode, these pins provide the clock recovered from the signal received on RTIPn/RRINGn. The
receive data (RDn in Single Rail Mode or RDPn/RDNn in Dual Rail Mode) is updated on the active edge of RCLKn. The
active edge is selected by the RCLK_SEL bit (RCF0, 28H...).
If clock recovery is bypassed, RCLKn is the exclusive OR(XOR) output of the Dual Rail sliced data RDPn and RDNn.
This signal can be used in the applications with external clock recovery circuitry.
TDPn
0
0
1
1
Transmit and Receive Digital Data Interface
TDNn
0
1
0
1
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
Space
Positive Pulse
Negative Pulse
Space
Output Pulse
11
Description
1
and the TCLKn missing inter-
February 5, 2009