IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 23

• Manufacturer Part Number: IDT82P5088BBG
• Description: IC LIU T1/E1/J1 OCTAL 256PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P5088BBG

• Includes: Integrated Clock Adapter
• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Power (watts): 2.57W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

TJA_IS bit. When the TJA_IS bit (INTS1, 3BH...) is ‘1’, an interrupt will
be reported on the INT pin if enabled by the TJA_IE bit (INTENC1,
34H...).
enabled by setting the TJA_LIMT bit (TJACF, 21H...). When the JA-
Limit function is enabled, the speed of the outgoing data will be adjusted
automatically if the FIFO is close to its full or emptiness. The criteria of
speed adjustment start are listed in Table 6. Though the LA-Limit func-
tion can reduce the possibility of FIFO overflow and underflow, the
quality of jitter attenuation is deteriorated.
interval between the read and write pointer of the FIFO or the peak-peak
interval between the read and write pointer of the FIFO can be indicated
in the TJITT[6:0] bits. When the TJITT_TEST bit is ‘0’, the current
interval between the read and write pointer of the FIFO will be written
into the TJITT[6:0] bits. When the TJITT_TEST bit is ‘1’, the current
interval is compared with the old one in the TJITT[6:0] bits and the larger
one will be indicated by the TJITT[6:0] bits.
FUNCTIONAL DESCRIPTION
IDT82P5088
To avoid overflowing or underflowing, the JA-Limit function can be
Selected by the TJITT_TEST bit (TJACF, 21H...), the real time
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
23
G.703, G.736 - 739, G.823, G.824, ETSI 300011, ETSI TBR 12/13,
AT&T TR62411, TR43802, TR-TSY 009, TR-TSY 253, TR-TRY 499
standards. Refer to Chapter 7.10 Jitter Tolerance and Chapter 7.10
Jitter Tolerance for details.
Table-15 Related Bit / Register In Chapter 3.2.6
TJA_DP[1:0]
TJITT_TEST
TJA_LIMT
TJITT[6:0]
The performance of Receive Jitter Attenuator meets the ITUT I.431,
TJA_BW
TJA_IS
TJA_IE
TJA_E
Bit
Transmit Jitter Attenuation Configura-
Transmit Jitter Measure Value Indica-
Interrupt Enable Control 1
Interrupt Status 1
Register
tion
tion
February 5, 2009
Address (Hex)
X21H
X3BH
X34H
X38H