IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 4
IDT82P5088BBG
Manufacturer Part Number
IDT82P5088BBG
Description
IC LIU T1/E1/J1 OCTAL 256PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82P5088BBG.pdf
(81 pages)
Specifications of IDT82P5088BBG
Includes
Integrated Clock Adapter
Function
Line Interface Unit (LIU)
Interface
E1, J1, T1
Number Of Circuits
8
Voltage - Supply
1.8V, 3.3V
Power (watts)
2.57W
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82P5088BBG
Manufacturer:
IDT
Quantity:
170
Company:
Part Number:
IDT82P5088BBG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT82P5088BBG
Manufacturer:
IDT
Quantity:
20 000
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5
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Tables of Contents
IDT82P5088
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
PROGRAMMING INFORMATION .............................................................................................. 40
4.1
4.2
4.3
IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 60
5.1
5.2
TEST SPECIFICATIONS ............................................................................................................ 64
3.5.4 INBAND LOOPBACK.............................................................................................. 33
ERROR DETECTION/COUNTING AND INSERTION ...................................................... 34
3.6.1 DEFINITION OF LINE CODING ERROR ............................................................... 34
3.6.2 ERROR DETECTION AND COUNTING ................................................................ 34
3.6.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 35
LINE DRIVER FAILURE MONITORING ........................................................................... 35
CLOCK GENERATOR AND TCLK ................................................................................... 36
3.8.1 CLOCK GENERATOR............................................................................................ 36
3.8.2 TRANSMIT CLOCK (TCLK).................................................................................... 36
MICROPROCESSOR INTERFACE ................................................................................. 37
3.9.1 SPI Mode ................................................................................................................ 37
3.9.2 Parallel Microprocessor Interface ........................................................................... 37
INTERRUPT HANDLING .................................................................................................. 38
GENERAL PURPOSE I/O ................................................................................................ 39
RESET OPERATION ........................................................................................................ 39
POWER SUPPLY ............................................................................................................. 39
REGISTER LIST AND MAP ............................................................................................. 40
RESERVED REGISTERS ................................................................................................ 40
REGISTER DESCRIPTION .............................................................................................. 42
4.3.1 GLOBAL REGISTERS............................................................................................ 42
4.3.2 PER CHANNEL CONTROL REGISTERS .............................................................. 44
4.3.3 TRANSMIT PATH CONTROL REGISTERS........................................................... 44
4.3.4 RECEIVE PATH CONTROL REGISTERS ............................................................. 47
4.3.5 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 49
4.3.6 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 52
4.3.7 INTERRUPT CONTROL REGISTERS ................................................................... 52
4.3.8 LINE STATUS REGISTERS ................................................................................... 55
4.3.9 INTERRUPT STATUS REGISTERS ...................................................................... 58
4.3.10 COUNTER REGISTERS ........................................................................................ 59
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 61
JTAG DATA REGISTER ................................................................................................... 61
5.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 61
5.2.2 BYPASS REGISTER (BR)...................................................................................... 61
5.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 61
5.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 62
3.5.4.1 Transmit Activate/Deactivate Loopback Code......................................... 33
3.5.4.2 Receive Activate/Deactivate Loopback Code.......................................... 33
3.5.4.3 Automatic Remote Loopback .................................................................. 33
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
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February 5, 2009