IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 47

• Manufacturer Part Number: IDT82P5088BBG
• Description: IC LIU T1/E1/J1 OCTAL 256PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P5088BBG

• Includes: Integrated Clock Adapter
• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Power (watts): 2.57W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

4.3.4
Table-44 RJACF: Jitter Attenuator Configuration Register for Receive Path
Table-45 RCF0: Receiver Configuration Register 0 for Receive Path
PROGRAMMING INFORMATION
IDT82P5088
RJITT_TEST
RJA_DP[1:0]
RCLK_SEL
RJA_LIMIT
R_MD[1:0]
RJA_BW
RD_INV
Symbol
Symbol
R_OFF
RJA_E
RECEIVE PATH CONTROL REGISTERS
-
-
(R/W, Address = X28H)
(R/W, Address = X27H)
7-6
2-1
7-5
1-0
Bit
Bit
4
3
2
5
4
3
0
Default
Default
000
00
00
00
00
1
0
0
0
0
0
Reserved
This bit selects jitter measure mode
= 0: real time mode (update jitter measuring value each received clock cycle)
= 1: accumulation mode (measuring p-p value of jitter since last read)
Wide Jitter Attenuation bandwidth
= 0: normal mode
= 1: JA limit mode
Jitter Attenuator configuration
= 0: JA not used
= 1: JA enabled
Jitter Attenuator depth selection
= 00: 128 bits
= 01: 64 bits
= 10/11: 32 bits
Jitter transfer function bandwidth selection
Reserved
Receiver power down enable
= 0: Receiver power up
= 1: Receiver power down
Receive data invert
= 0: data on RDn or RDPn/RDNn is active high
= 1: data on RDn or RDPn/RDNn is active low
Receive clock edge select (this bit is ignored in slicer mode)
= 0: data on RDn or RDPn/RDNn is updated on the rising edges of RCLKn
= 1: data on RDn or RDPn/RDNn is updated on the falling edges of RCLKn
Receiver path decoding selection
= 00: receive data is HDB3 (E1) / B8ZS (T1/J1) decoded and output on RDn with single rail NRZ format
= 01: receive data is AMI decoded and output on RDn with single rail NRZ format
= 10: decoder is bypassed, re-timed dual rail data with NRZ format output on RDPn/RDNn (dual rail mode with
clock recovery)
= 11: both CDR and decoder blocks are bypassed, slicer data with RZ format output on RDPn/RDNn (slicer mode)
JABW
0
1
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
47
1.26 Hz
T1/J1
5 Hz
Description
Description
6.77 Hz
0.87 Hz
E1
February 5, 2009