IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 62

• Manufacturer Part Number: IDT82P5088BBG
• Description: IC LIU T1/E1/J1 OCTAL 256PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P5088BBG

• Includes: Integrated Clock Adapter
• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Power (watts): 2.57W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

5.2.4
shows its state diagram following the description of each state. Note that
the figure contains two main branches to access either the data or instruc-
Table-70 TAP Controller State Description
IEEE STD 1149.1 JTAG TEST ACCESS PORT
IDT82P5088
The TAP controller is a 16-state synchronous state machine.
Test Logic Reset
Select-DR-Scan
Select-IR-Scan
Run-Test/Idle
Capture-DR
Update-DR
Capture-IR
Pause-DR
Exit1-DR
Exit2-DR
Shift-DR
TEST ACCESS PORT CONTROLLER
Shift-IR
STATE
In this state, the test logic is disabled. The device is set to normal operation. During initialization, the device initializes the instruction register
with the IDCODE instruction. Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the
TMS input is held high for at least 5 rising edges of TCK. The controller remains in this state while TMS is high. The device processor auto-
matically enters this state at power-up.
This is a controller state between scan operations. Once in this state, the controller remains in the state as long as TMS is held low. The
instruction register and all test data registers retain their previous state. When TMS is high and a rising edge is applied to TCK, the control-
ler moves to the Select-DR state.
This is a temporary controller state and the instruction does not change in this state. The test data register selected by the current instruc-
tion retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Cap-
ture-DR state and a scan sequence for the selected test data register is initiated. If TMS is held high and a rising edge applied to TCK, the
controller moves to the Select-IR-Scan state.
In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or SAMPLE/PRELOAD. The instruc-
tion does not change in this state. The other test data registers, which do not have parallel input, are not changed. When the TAP controller
is in this state and a rising edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or the Shift-DR state if TMS is low.
In this controller state, the test data register connected between TDI and TDO as a result of the current instruction shifts data on stage
toward its serial output on each rising edge of TCK. The instruction does not change in this state. When the TAP controller is in this state
and a rising edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or remains in the Shift-DR state if TMS is low.
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-DR
state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this
state.
The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between TDI
and TDO. For example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test
sequence. The test data register selected by the current instruction retains its previous value and the instruction does not change during this
state. The controller remains in this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller
moves to the Exit2-DR state.
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-DR
state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this
state.
The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in response to the EXTEST
and SAMPLE/PRELOAD instructions. When the TAP controller is in this state and the Boundary Scan Register is selected, data is latched
into the parallel output of this register from the shift-register path on the falling edge of TCK. The data held at the latched parallel output
changes only in this state. All shift-register stages in the test data register selected by the current instruction retain their previous value and
the instruction does not change during this state.
This is a temporary controller state. The test data register selected by the current instruction retains its previous state. If TMS is held low
and a rising edge is applied to TCK when in this state, the controller moves into the Capture-IR state, and a scan sequence for the instruc-
tion register is initiated. If TMS is held high and a rising edge is applied to TCK, the controller moves to the Test-Logic-Reset state. The
instruction does not change during this state.
In this controller state, the shift register contained in the instruction register loads a fixed value of '100' on the rising edge of TCK. This sup-
ports fault-isolation of the board-level serial test data path. Data registers selected by the current instruction retain their value and the
instruction does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters
the Exit1-IR state if TMS is held high, or the Shift-IR state if TMS is held low.
In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data one stage towards its
serial output on each rising edge of TCK. The test data register selected by the current instruction retains its previous value and the instruc-
tion does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-
IR state if TMS is held high, or remains in the Shift-IR state if TMS is held low.
Figure-24
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
62
tion registers. The value shown next to each state transition in this figure
states the value present at TMS at each rising edge of TCK. Please refer
to
DESCRIPTION
Table-70
for details of the state description.
February 5, 2009