IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 8
IDT82P5088BBG
Manufacturer Part Number
IDT82P5088BBG
Description
IC LIU T1/E1/J1 OCTAL 256PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82P5088BBG.pdf
(81 pages)
Specifications of IDT82P5088BBG
Includes
Integrated Clock Adapter
Function
Line Interface Unit (LIU)
Interface
E1, J1, T1
Number Of Circuits
8
Voltage - Supply
1.8V, 3.3V
Power (watts)
2.57W
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82P5088BBG
Manufacturer:
IDT
Quantity:
170
Company:
Part Number:
IDT82P5088BBG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT82P5088BBG
Manufacturer:
IDT
Quantity:
20 000
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Figure-36
List Of Figures
IDT82P5088
Block Diagram ................................................................................................................. 2
IDT82P5088 PBGA256 Package Pin Assignment (top view) ......................................... 9
E1 Waveform Template Diagram .................................................................................. 17
E1 Pulse Template Test Circuit ..................................................................................... 17
DSX-1 Waveform Template .......................................................................................... 18
T1 Pulse Template Test Circuit ..................................................................................... 18
Jitter Attenuator ............................................................................................................. 22
Receive Path Function Block Diagram .......................................................................... 24
Transmit/Receive Line Circuit ....................................................................................... 24
Monitoring Receive Line in Another Chip ...................................................................... 25
Monitor Transmit Line in Another Chip .......................................................................... 25
G.772 Monitoring Diagram ............................................................................................ 26
LOS Declare and Clear ................................................................................................. 27
Analog Loopback .......................................................................................................... 31
Digital Loopback ............................................................................................................ 31
Remote Loopback ......................................................................................................... 32
Auto Report Mode ......................................................................................................... 34
Manual Report Mode ..................................................................................................... 35
Clock Generator ............................................................................................................ 36
TCLK Operation Flowchart ............................................................................................ 36
Read Operation In SPI Mode ........................................................................................ 37
Write Operation In SPI Mode ........................................................................................ 37
JTAG Architecture ......................................................................................................... 60
JTAG State Diagram ..................................................................................................... 63
Transmit System Interface Timing ................................................................................ 70
Receive System Interface Timing ................................................................................. 70
T1/J1 Jitter Tolerance Performance Requirement ........................................................ 71
E1 Jitter Tolerance Performance Requirement ............................................................. 72
T1/J1 Jitter Transfer Performance Requirement (AT&T62411 / GR-253-CORE / TR-TSY-
74
E1 Jitter Transfer Performance Requirement (G.736) .................................................. 75
JTAG Interface Timing .................................................................................................. 76
Motorola Non-Multiplexed Mode Read Cycle ................................................................ 77
Motorola Non-Multiplexed Mode Write Cycle ................................................................ 78
Intel Non-Multiplexed Mode Read Cycle ....................................................................... 79
Intel Non-Multiplexed Mode Write Cycle ....................................................................... 79
SPI Timing Diagram ...................................................................................................... 80
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
8
List Of Figures
February 5, 2009