NCP5901MNTBG ON Semiconductor, NCP5901MNTBG Datasheet - Page 7

• Manufacturer Part Number: NCP5901MNTBG
• Description: IC MOSFET DVR SYNC VR12 8-DFN
• Manufacturer: ON Semiconductor
• Type: VR12 Compatible Synchronous Buck MOSFET Driverr

Specifications of NCP5901MNTBG

• Configuration: High and Low Side, Synchronous
• Input Type: Non-Inverting
• Delay Time: 25ns
• Number Of Configurations: 1
• Number Of Outputs: 2
• Mounting Type: Surface Mount
• Package / Case: 8-DFN
• Product: MOSFET Gate Drivers
• Propagation Delay Time: 25 ns
• Mounting Style: SMD/SMT
• Number Of Drivers: 1
• Output Voltage: 35 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Peak: -
• High Side Voltage - Max (bootstrap): -
• Voltage - Supply: -
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

designed for driving N−channel MOSFETs in a synchronous
buck converter topology. The NCP5901 is designed to work
with ON Semiconductor’s NCP6131 multi−phase controller.
This gate driver is optimized for desktop applications.
Undervoltage Lockout
4.5 V during startup. The PWM signals will control the gate
status when V
250 mV below the threshold, the output gate will be forced
low until input voltage V
Power−On Reset
avoid abnormal status driving the startup condition. When
the initial soft−start voltage is higher than 2.75 V, the gate
driver will monitor the switching node SW pin. If SW pin
high than 2.25 V, bottom gate will be force to high for
discharge the output capacitor. The fault mode will be latch
and EN pin will force to be low, unless the driver is recycle.
When input voltage is higher than 4.5 V, and EN goes high,
the gate driver will normal operation, top gate driver
DRVH and bottom gate driver will follow the PWM signal
decode to a status.
Bi−directional EN Signal
Lockout will de−assert the EN pin, which will pull down
the DRON pin of controller as well. Thus the controller will
be shut down consequently.
PWM Input and Zero Cross Detect (ZCD)
state of DRVH and DRVL.
adaptive non−overlap delay. When PWM is set low, DRVL
will be set high after the adaptive non−overlap delay.
low, and after the adaptive non−overlap delay, DRVL will
be set high. DRVL remains high during the ZCD blanking
time. When the timer is expired, the SW pin will be
monitored for zero cross detection. After the detection, the
DRVL will be set low.
Adaptive Nonoverlap
shoot through damage the power MOSFETs. When the
PWM signal pull high, DRVL will go low after a
propagation delay, the controller will monitors the
switching node (SWN) pin voltage and the gate voltage of
the MOSFET to know the status of the MOSFET. When the
low side MOSFET status is off an internal timer will delay
turn on of the high–side MOSFET. When the PWM pull
The NCP5901 gate driver is a single phase MOSFET driver
The DRVH and DRVL are held low until V
Power−On Reset feature is used to protect a gate driver
Fault modes such as Power−On Reset and Undervoltage
The PWM input, along with EN and ZCD, control the
When PWM is set high, DRVH will be set high after the
When the PWM is set to the mid state, DRVH will be set
The nonoverlap dead time control is used to avoid the
CC
threshold is exceeded. If V
CC
rises above the startup threshold.
APPLICATIONS INFORMATION
CC
decreases to
CC
reaches
http://onsemi.com
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low, gate DRVH will go low after the propagation delay
(tpd
on the total gate charge of the high−side MOSFET. A timer
will be triggered once the high side MOSFET is turn off to
delay the turn on the low−side MOSFET.
Low−Side Driver Timeout
signal and turns off the Q1 high−side switch with a few 10
ns delay (t
signal. When Q1is turned off, DRVL is allowed to go high,
Q2 turns on, and the SW node voltage collapses to zero. But
in a fault condition such as a high−side Q1 switch
drain−source short circuit, the SW node cannot fall to zero,
even when DRVH goes low. This driver has a timer circuit
to address this scenario. Every time the PWM goes low, a
DRVL on−time delay timer is triggered.
turn−on, the DRVL on−time delay circuit does it instead,
when it times out with t
that is, its drain is shorted to the source, Q2 turns on and
creates a direct short circuit across the VDCIN voltage rail.
The crowbar action causes the fuse in the VDCIN current
path to open. The opening of the fuse saves the load (CPU)
from potential damage that the high−side switch short
circuit could have caused.
Layout Guidelines
bootstrap and V
close as to the driver IC.
plane can provide a good return path for gate drives and
reduce the ground noise. The thermal slug should be tied to
the ground plane for good heat dissipation. To minimize the
ground loop for low side MOSFET, the driver GND pin
should be close to the low−side MOSFET source pin. The
gate drive trace should be routed to minimize the length,
the minimum width is 20 mils.
Gate Driver Power Loss Calculation
and quiescent power loss.
dissipation of the gate driver. Where Q
charge for each main MOSFET and Q
charge for each synchronous MOSFET.
P
of the driver.
DRV
The time to turn off the high side MOSFET is depending
In normal operation, the DRVH signal tracks the PWM
If the SW node voltage does not trigger a low−side
Layout for DC−DC converter is very important. The
Connect GND pin to local ground plane. The ground
The gate driver power loss consists of the gate drive loss
The equation below can be used to calculate the power
Also shown is the standby dissipation factor (I
DRVH
+ [
2
f
).
pdlDRVH
SW
n
CC
n
) following the falling edge of the input
bypass capacitors should be placed as
MF
SW(TO)
Q
GMF
delay. If Q1 is still turned on,
) n
SF
GMF
GSF
Q
GSF
is the total gate
is the total gate
) I
CC
CC
]
⋅ V
CC
V
CC
)