MC10XS3535PNA Freescale Semiconductor, MC10XS3535PNA Datasheet - Page 27

• Manufacturer Part Number: MC10XS3535PNA
• Description: IC SWITCH HIGHSIDE 24PQFN
• Manufacturer: Freescale Semiconductor
• Type: High Side Switchr

Specifications of MC10XS3535PNA

• Number Of Outputs: 5
• Rds (on): 10 mOhm, 35 mOhm
• Internal Switch(s): No
• Voltage - Input: 7 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-PQFN, 24-PowerQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current Limit: -

ADDRESS 00000 — INITIALIZATION
statuses, choose one of the six outputs current recopy, load
the H7 bulbs profile for OUT2 only, enable the FOG pin and
synchronize the switching phases between different devices.
The register bits D1 and D0 determine the content of the 16
bits of the next SO data. (Refer to the section entitled
Output Communication (Device Status Return Data)
ADDRESS 00001 — CONFIGURATION OL
load detection for LEDs in Normal Mode (OLLEDn in
page 26) and to active the LED Control.
circuit for LED is activated for output 1. When bit D0 is set to
logic [0], open load detection circuit for standard bulbs is
activated for output 1.
for output 1.
ADDRESS 00010 — CONFIGURATION PRESCALER
AND SR
The Configuration Prescaler when D9 bit is set to logic [0] and
Configuration SR when D9 bit is set to logic [1].
PWM clock prescaler per output. When the corresponding
PR bit is set to logic [1], the clock prescaler (reference clock
divided by 2) is activated for the dedicated output.
slew-rate by a factor of 2. When the corresponding SR bit is
set to logic [1], the output switching time is divided by 2 for the
dedicated output.
Analog Integrated Circuit Device Data
Freescale Semiconductor
D6 (PWM sync) = 0, No synchronization
D6 (PWM sync) = 1, Synchronization on CSB positive edge
D5 (Xenon) = 0, Xenon
D5 (Xenon) = 1, H7 Bulb
D7 (FOGen) = 0, FOG pin does not control the output 4
D7 (FOGen) = 1, FOG input controls the output 4
D15
The Initialization register is used to read the various
The Configuration OL register is used to enable the open
When bit D0 is set to logic [1], the open load detection
When bit D5 is set to logic [1], the LED Control is activated
Two configuration registers are available at this address.
The Configuration Prescaler register is used to enable the
The SR Prescaler register is used to increase the output
0
D14
0
SI Address
D13
0
D12
0
D11
0
D10
WD
Table 8. Initialization Register
D9
0
Table
Serial
7,
D8
0
FOGen
D4, D3, D2 (MUX2, MUX1, MUX0) = 000, No current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 001, OUT1 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 010, OUT2 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 011, OUT3 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 100, OUT4 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 101, OUT5 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 110, External Switch current
sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 111, Temperature analog
feedback
D7
beginning on page 28.)
initialization.
long as the WD bit (D10) of an incoming SPI message is
toggled within the minimum watchdog timeout period
(WDTO), the device will operate normally. If an internal
watchdog timeout occurs before the WD bit is toggled, the
device will revert to Fail mode. All registers are cleared. To
exit the Fail mode, send valid SPI communication with
WD bit = 1.
ADDRESS 00011 — CONFIGURATION CSNS
disable the high over-current shutdown phase (OCHI1 and
OCHI2 dynamic levels) in order to activate immediately the
current sense analog feedback.
synchronization signal is reported on FETOUT output pin.
the output is only protected with OCLO level. And the current
sense is immediately available if it is selected through SPI, as
described in
automatically reset at each corresponding ONoff bit transition
from logic [1] to [0] and in case of over-temperature or over-
current fault. All NO_OCHI bits are also reset in case of
under-voltage fault detection.
ADDRESS 01001 — CONTROL OUT1
Table
The watchdog timeout is specified by
The Configuration Current Sense register is used to
When bit D9 is set to logic [1], the current sense
When the corresponding NO_OCHI bit is set to logic [1],
Bits D9 and D8 control the switching phases as shown in
9.
PWM
sync
D6
Figures
SI Data
Xenon
D9 : D8
D5
Table 9. Switching Phases
00
01
13. The NO_OCHI bit per output is
MUX2
D4
Table 8
LOGIC COMMANDS AND REGISTERS
FUNCTIONAL DEVICE OPERATION
MUX1
D3
describes the register of
PWM Phase
MUX0
t
D2
WDTO
90°
0°
parameter. As
SOA1
D1
10XS3535
SOA0
D0
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