RT8055GQW Richtek USA Inc, RT8055GQW Datasheet - Page 11

• Manufacturer Part Number: RT8055GQW
• Description: IC DCDC CONV STP-DN SYNC 10WDFN
• Manufacturer: Richtek USA Inc
• Type: Step-Down (Buck), PWM - Current Moder

Specifications of RT8055GQW

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.8 V ~ 5 V
• Current - Output: 3A
• Frequency - Switching: 300kHz ~ 2MHz
• Voltage - Input: 2.6 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-WFDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

wires, a load step at the output can induce ringing at the
input, V
and be
inrush of current through the long wires can potentially
cause a voltage spike at V
part.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
P
where T
the ambient temperature, and θ
thermal resistance.
For recommended operating condition specifications of
the RT8055, the maximum junction temperature is 125°C
and T
thermal resistance, θ
(Exposed Pad) packages, the thermal resistance, θ
75°C/W on a standard JEDEC 51-7 four-layer thermal test
board. For WDFN-10L 3x3 packages, the thermal
resistance, θ
four-layer thermal test board. The maximum power
dissipation at T
formulas :
P
SOP-8 (Exposed Pad) package
P
WDFN-10L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
resistance, θ
curves in Figure 4 allow the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
DS8055-03 March 2011
D(MAX)
D(MAX)
D(MAX)
A
is the ambient temperature. The junction to ambient
= (T
DD
mistaken as loop instability. At worst, a sudden
J(MAX)
= (125°C − 25°C) / (75°C/W) = 1.333W for
= (125°C − 25°C) / (70°C/W) = 1.429W for
. At best, this ringing can couple to the output
J(MAX)
JA
JA
is the maximum junction temperature, T
A
. For the RT8055 packages, the derating
, is 70°C/W on a standard JEDEC 51-7
= 25°C can be calculated by the following
− T
A
JA
) / θ
, is layout dependent. For SOP-8
JA
IN
large enough to damage the
JA
is the junction to ambient
J(MAX)
and thermal
JA
A
, is
is
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8055.
A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the GND pin at one point that is then connected to
the PGND pin close to the IC. The exposed pad should
be connected to GND.
Connect the terminal of the input capacitor(s), C
close as possible to the PVDD pin. This capacitor
provides the AC current into the internal power
MOSFETs.
LX node is with high frequency voltage swing and should
be kept within small area. Keep all sensitive small-signal
nodes away from the LX node to prevent stray capacitive
noise pick-up.
Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of powercomponents.
You can connect the copper areas to any DC net (PVDD,
VDD, VOUT, PGND, GND, or any other DC rail in your
system).
Connect the FB pin directly to the feedback resistors.
The resistor divider must be connected between V
and GND.
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Figure 3. Derating Curves for RT8055 Package
0
SOP-8 (Exposed Pad)
25
Ambient Temperature (°C)
50
WDFN-10L 3x3
75
Four-Layer PCB
RT8055
www.richtek.com
100
IN
125
, as
OUT
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