CP2112EK Silicon Laboratories Inc, CP2112EK Datasheet - Page 11

• Manufacturer Part Number: CP2112EK
• Description: KIT EVAL FOR CP2112
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2112EK

• Main Purpose: Interface, USB 2.0 to SMBus Bridge
• Embedded: No
• Utilized Ic / Part: CP2112
• Primary Attributes: Full Speed (12Mbps)
• Secondary Attributes: LED Status Indicators
• Interface Type: USB
• Operating Supply Voltage: 3.3 V
• Product: Interface Development Tools
• For Use With/related Products: CP2112
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-2010

Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
Dimension
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder-mask defined (NSMD). Clearance between the solder
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch should be used for the center
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for small
C1
C2
X1
E
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
to assure good solder paste release.
pad.
body components.
Figure 4. QFN-24 Recommended PCB Land Pattern
Table 9. QFN-24 PCB Land Pattern Dimensions
3.90
3.90
0.20
Min
0.50 BSC
Max
4.00
4.00
0.30
Rev. 1.0
Dimension
X2
Y1
Y2
2.70
0.65
2.70
Min
Max
2.80
0.75
2.80
CP2112
11