ZL6100EVAL1Z Intersil, ZL6100EVAL1Z Datasheet
ZL6100EVAL1Z
Specifications of ZL6100EVAL1Z
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ZL6100EVAL1Z Summary of contents
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... Zilker Labs evaluation board that supports the Digital DC (DDC) bus. Figure 1 shows a functional block diagram of the ZL6100EVAL1Z board. The SMBus address is selectable through a jumper on the top side of the board. All power to the board (VIN and I changing the jumpers. ...
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... The hardware enable function is controlled by a toggle switch on the ZL6100EVAL1Z board. The power-good (PG) LEDs indicate the correct state of PG when external power is applied to the ZL6100EVAL1Z board. The right angle headers at opposite ends of the board are for connecting a USB to SMBus adapter board or for daisy chaining of multiple evaluation boards ...
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... ZL6100EVAL1Z BOARD SCHEMATICS JP1 JP1 PG_0 1 PG_0 Rework across 3 Q1/1 and Q1/2 4 HW_EN R1 R1 100k 100k C50 C50 100p 100p SG V25 V25 DDC DDC CFG CFG DLY0 DLY0 DLY1 DLY1 DGND VDD SYNC SYNC SYNC BST 3 SA0 GH 4 SA1 SW ILIM0 5 ILIM0 ...
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... LOSS OF PROFITS), OR OTHERWISE, RESULTING FROM THE REFERENCE DESIGNS OR ANY USE THEREOF. Any use of such reference designs is at your own risk and you agree to indemnify Zilker Labs for any damages resulting from such use FIGURE 3. ZL6100EVAL1Z INTERFACE CIRCUITRY VIN P2 P2 C30 C30 ...
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... ZL6100EVAL1Z BOARD LAYOUT - 4 LAYERS 5 Application Note 1493 FIGURE 4. PCB - TOP LAYER AN1493.0 September 4, 2009 ...
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... ZL6100EVAL1Z BOARD LAYOUT - 4 LAYERS 6 Application Note 1493 FIGURE 5. PCB - INNER LAYER 1 (TOP VIEW) (Continued) AN1493.0 September 4, 2009 ...
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... ZL6100EVAL1Z BOARD LAYOUT - 4 LAYERS 7 Application Note 1493 FIGURE 6. PCB - INNER LAYER 2 (TOP VIEW) (Continued) AN1493.0 September 4, 2009 ...
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... ZL6100EVAL1Z BOARD LAYOUT - 4 LAYERS 8 Application Note 1493 FIGURE 7. PCB - BOTTOM LAYER (TOP VIEW) (Continued) AN1493.0 September 4, 2009 ...
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... ZL6100EVAL1Z BOARD LAYOUT - 4 LAYERS 9 Application Note 1493 FIGURE 8. BOARD FABRICATION NOTES (Continued) AN1493.0 September 4, 2009 ...
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Bill of Materials REFERENCE PART NUMBER QTY UNIT DESIGNATOR H1045-00101 C50 100V5-T H1045-00104 C39, C41, C43 10V10-T H1045-00104 C29, C46 25V10-T H1045-00105 C11, C17, C42 25V10-T H1045-00106 C10, C26, C27 ...
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... P1, P2 (COVER BOTTOMS OF POST ENDS) NOTE NOT CLEAN-INSTALL AFTER ASSY. 11 Application Note 1493 DESCRIPTION IC-DIGITAL DC/DC CONTROLLER, 36P, INTERSIL QFN, 6x6, ROHS TRANSIST-MOS, DUAL N-CHANNEL, FAIRCHILD SMD, SC70-6, 25V, 220mA, ROHS TRANSIST-MOS,DUAL P-CHANNEL, 6P, FAIRCHILD SC70-6, -25V, -0.41A, ROHS TRANSISTOR-MOS, N-CHANNEL, 8P, ...
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... Default Configuration Text The following text is loaded into the ZL6100 device on the ZL6100EVAL1Z as default settings. Each PMBus command is loaded via the PowerNavigator software. The # symbol is used for a comment line. # This configuration is intended for Zilker Labs ZL6100EV1 # ZL Configuration File Revision 2 # Schematic revision level # ZL Author B ...
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... Measured Data The following data was acquired using a ZL6100EVAL1Z Rev 2 evaluation board. Adaptive diode emulation and adaptive frequency modes are disabled for these efficiency measurements OUTPUT CURRENT (A) FIGURE 9. EFFICIENCY 12V 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 TIME (s) FIGURE 11 ...
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... AN1493.0 Converted to new Intersil template from Word document. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com ...