ZL6100EVAL1Z Intersil, ZL6100EVAL1Z Datasheet

no-image

ZL6100EVAL1Z

Manufacturer Part Number
ZL6100EVAL1Z
Description
EVAL BOARD USB ZL6100
Manufacturer
Intersil
Datasheets

Specifications of ZL6100EVAL1Z

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ZL6100EVAL1Z
Manufacturer:
Intersil
Quantity:
4
ZL6100EVAL1Z Evaluation Board
The ZL6100 is an integrated mixed-signal power
conversion and management IC that combines an
efficient step-down DC/DC converter with key power and
thermal management functions in a single package. The
ZL6100 incorporates current sharing and adaptive
efficiency-optimization algorithms to provide a flexible,
efficient power IC building block.
The ZL6100EVAL1Z platform is a 4-layer board
demonstrating a 15A synchronous buck converter.
Sequencing, tracking, margining, plus other features can
be evaluated using this board.
A USB to SMBus adapter board can be used to connect
the evaluation board to a PC. The PMBus command set is
accessed by using the Zilker Labs PowerNavigator™
evaluation software from a PC running Microsoft
Windows.
Key Features
• 15A Synchronous Buck Converter
• Optimized for Small Circuit Footprint and Dynamic
• Configurable through SMBus
• Onboard Enable Switch
• Power-Good Indicator
Ordering Information
ZL6100EVAL1Z ZL6100 Evaluation Kit (EVB, USB Adapter,
September 4, 2009
AN1493.0
Response
NUMBER
PART
S MB us
TRA CK
S Y NC
V
DDC
IN
Cable, Software)
J10
ENABLE
1
SW1
DESCRIPTION
FIGURE 1. ZL6100EVAL1Z BLOCK DIAGRAM
1-888-INTERSIL or 1-888-468-3774
Application Note 1493
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
E N
S Y NC
S MB us
DDC
ZL6100
VTRK
Target Specifications
• V
• V
• f
• Efficiency: 86% at 10A
• Output Ripple: ±1%
• Dynamic Response: ±3%
• Board Temperature: +25°C
Functional Description
The ZL6100EVAL1Z provides all circuitry required to
demonstrate the features of the ZL6100. The
ZL6100EVAL1Z has a functionally-optimized ZL6100
circuit layout that allows efficient operation up to the
maximum output current. Power and load connections
are provided through plug-in sockets.
A majority of the features of the ZL6100 such as
soft-start delay and ramp times, supply sequencing,
voltage tracking, and voltage margining are available on
this evaluation board. For voltage tracking and
sequencing evaluation, the board can be connected to
any other Zilker Labs evaluation board that supports the
Digital DC (DDC) bus.
Figure 1 shows a functional block diagram of the
ZL6100EVAL1Z board. The SMBus address is selectable
through a jumper on the top side of the board. All power
to the board (VIN and I
changing the jumpers.
(50% to 100% to 50% load step, di/dt = 2.5A/µs)
All other trademarks mentioned are the property of their respective owners.
sw
IN
OUT
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
= 400kHz
= 12V
= 1.2V/15A (20A max)
Copyright Intersil Americas Inc. 2009. All Rights Reserved
PG
2
C bus) must be removed before
J11
S Y NC
DDC
S MB us
TRA CK
P G
V
OUT

Related parts for ZL6100EVAL1Z

ZL6100EVAL1Z Summary of contents

Page 1

... Zilker Labs evaluation board that supports the Digital DC (DDC) bus. Figure 1 shows a functional block diagram of the ZL6100EVAL1Z board. The SMBus address is selectable through a jumper on the top side of the board. All power to the board (VIN and I changing the jumpers. ...

Page 2

... The hardware enable function is controlled by a toggle switch on the ZL6100EVAL1Z board. The power-good (PG) LEDs indicate the correct state of PG when external power is applied to the ZL6100EVAL1Z board. The right angle headers at opposite ends of the board are for connecting a USB to SMBus adapter board or for daisy chaining of multiple evaluation boards ...

Page 3

... ZL6100EVAL1Z BOARD SCHEMATICS JP1 JP1 PG_0 1 PG_0 Rework across 3 Q1/1 and Q1/2 4 HW_EN R1 R1 100k 100k C50 C50 100p 100p SG V25 V25 DDC DDC CFG CFG DLY0 DLY0 DLY1 DLY1 DGND VDD SYNC SYNC SYNC BST 3 SA0 GH 4 SA1 SW ILIM0 5 ILIM0 ...

Page 4

... LOSS OF PROFITS), OR OTHERWISE, RESULTING FROM THE REFERENCE DESIGNS OR ANY USE THEREOF. Any use of such reference designs is at your own risk and you agree to indemnify Zilker Labs for any damages resulting from such use FIGURE 3. ZL6100EVAL1Z INTERFACE CIRCUITRY VIN P2 P2 C30 C30 ...

Page 5

... ZL6100EVAL1Z BOARD LAYOUT - 4 LAYERS 5 Application Note 1493 FIGURE 4. PCB - TOP LAYER AN1493.0 September 4, 2009 ...

Page 6

... ZL6100EVAL1Z BOARD LAYOUT - 4 LAYERS 6 Application Note 1493 FIGURE 5. PCB - INNER LAYER 1 (TOP VIEW) (Continued) AN1493.0 September 4, 2009 ...

Page 7

... ZL6100EVAL1Z BOARD LAYOUT - 4 LAYERS 7 Application Note 1493 FIGURE 6. PCB - INNER LAYER 2 (TOP VIEW) (Continued) AN1493.0 September 4, 2009 ...

Page 8

... ZL6100EVAL1Z BOARD LAYOUT - 4 LAYERS 8 Application Note 1493 FIGURE 7. PCB - BOTTOM LAYER (TOP VIEW) (Continued) AN1493.0 September 4, 2009 ...

Page 9

... ZL6100EVAL1Z BOARD LAYOUT - 4 LAYERS 9 Application Note 1493 FIGURE 8. BOARD FABRICATION NOTES (Continued) AN1493.0 September 4, 2009 ...

Page 10

Bill of Materials REFERENCE PART NUMBER QTY UNIT DESIGNATOR H1045-00101 C50 100V5-T H1045-00104 C39, C41, C43 10V10-T H1045-00104 C29, C46 25V10-T H1045-00105 C11, C17, C42 25V10-T H1045-00106 C10, C26, C27 ...

Page 11

... P1, P2 (COVER BOTTOMS OF POST ENDS) NOTE NOT CLEAN-INSTALL AFTER ASSY. 11 Application Note 1493 DESCRIPTION IC-DIGITAL DC/DC CONTROLLER, 36P, INTERSIL QFN, 6x6, ROHS TRANSIST-MOS, DUAL N-CHANNEL, FAIRCHILD SMD, SC70-6, 25V, 220mA, ROHS TRANSIST-MOS,DUAL P-CHANNEL, 6P, FAIRCHILD SC70-6, -25V, -0.41A, ROHS TRANSISTOR-MOS, N-CHANNEL, 8P, ...

Page 12

... Default Configuration Text The following text is loaded into the ZL6100 device on the ZL6100EVAL1Z as default settings. Each PMBus command is loaded via the PowerNavigator software. The # symbol is used for a comment line. # This configuration is intended for Zilker Labs ZL6100EV1 # ZL Configuration File Revision 2 # Schematic revision level # ZL Author B ...

Page 13

... Measured Data The following data was acquired using a ZL6100EVAL1Z Rev 2 evaluation board. Adaptive diode emulation and adaptive frequency modes are disabled for these efficiency measurements OUTPUT CURRENT (A) FIGURE 9. EFFICIENCY 12V 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 TIME (s) FIGURE 11 ...

Page 14

... AN1493.0 Converted to new Intersil template from Word document. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com ...

Related keywords