MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 127
![KIT DEVELOPMENT I.MX53](/photos/39/51/395134/4751369_sml.jpg)
MCIMX53-START
Manufacturer Part Number
MCIMX53-START
Description
KIT DEVELOPMENT I.MX53
Manufacturer
Freescale Semiconductor
Series
i.MX53r
Type
MCUr
Datasheets
1.MCIMX53-START.pdf
(2 pages)
2.MCIMX53-START.pdf
(180 pages)
3.MCIMX53-START.pdf
(204 pages)
Specifications of MCIMX53-START
Contents
Board
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
Cortex - A8
Silicon Core Number
I.MX5
Silicon Family Name
I.MX53
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
i.MX53
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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4.7.15
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 78
(SPDIF), including the timing of the modulating Rx clock (SRCK) for SPDIF in Rx mode and the timing
of the modulating Tx clock (STCLK) for SPDIF in Tx mode.
Freescale Semiconductor
1
2
SPDIFIN Skew: asynchronous inputs, no specs apply
SPDIFOUT output (Load = 50pf)
SPDIFOUT1 output (Load = 30pf)
Modulating Rx clock (SRCK) period
SRCK high period
SRCK low period
Modulating Tx clock (STCLK) period
STCLK high period
STCLK low period
SJ9
SJ10
SJ11
SJ12
SJ13
• Skew
• Transition rising
• Transition falling
• Skew
• Transition rising
• Transition falling
T
V
ID
DC
M
= mid-point voltage
= target frequency of SJC
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO high impedance
TRST assert time
TRST set-up time to TCK low
and Figures , show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format
SPDIF Timing Parameters
Characteristics
i.MX53xD Applications Processors for Consumer Products, Rev. 1
Parameter
Table 78. SPDIF Timing Parameters
Table 77. JTAG Timing (continued)
1,2
Symbol
stclkph
srckph
stclkpl
srckpl
stclkp
srckp
—
—
—
—
—
—
—
Timing Parameter Range
40.0
16.0
40.0
16.0
16.0
16.0
Min
—
—
—
—
—
—
—
Min
100
25
40
All Frequencies
—
—
Electrical Characteristics
Max
24.2
31.3
13.6
18.0
0.7
1.5
1.5
Max
—
—
—
—
—
—
44
44
—
—
—
Units
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
127
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