SX1231-31SKB915 Semtech, SX1231-31SKB915 Datasheet

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SX1231-31SKB915

Manufacturer Part Number
SX1231-31SKB915
Description
TVS
Manufacturer
Semtech
Datasheets

Specifications of SX1231-31SKB915

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SX1231 Transceiver
Low Power Integrated UHF Transceiver
The SX1231 is a highly integrated RF transceiver capable of
operation over a wide frequency range, including the 433,
868 and 915 MHz license-free ISM (Industry Scientific and
Medical) frequency bands. Its highly integrated architecture
allows for a minimum of external components whilst
maintaining maximum design flexibility. All major RF
communication parameters are programmable and most of
them can be dynamically set. The SX1231 offers the unique
advantage of programmable narrow-band and wide-band
communication modes without the need to modify external
components. The SX1231 is optimized for low power
consumption while offering high RF output power and
channelized operation. TrueRF™ technology enables a low-
cost external component count (elimination of the SAW
filter) whilst still satisfying ETSI and FCC regulations.
Rev 3 - April 2010
ADVANCED COMMUNICATIONS & SENSING
GENERAL DESCRIPTION
APPLICATIONS
MARKETS
Automated Meter Reading
Wireless Sensor Networks
Home and Building Automation
Wireless Alarm and Security Systems
Industrial Monitoring and Control
Europe: EN 300-220-1
North America: FCC Part 15.247, 15.249, 15.231
Narrow Korean and Japanese bands
PA_BOOST
VR_PA
RFIO
GND
PA1&2
PA0
Ramp &
Control
LNA
VBAT1&2
Power Distribution System
Differential
Single to
VR_ANA
Inductor
Loop
Filter
Tank
Frac-N PLL
Synthesizer
Division by
2, 4 or 6
32 MHz
Mixers
XTAL
XO
VR_DIG
Page 1
Modulators
Σ/Δ
KEY PRODUCT FEATURES
ORDERING INFORMATION
RSSI
GND
SX1231IMLTRT
High Sensitivity: down to -120 dBm at 1.2 kbps
High Selectivity: 16-tap FIR Channel Filter
Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm,
80 dB Blocking Immunity, no Image Frequency response
Low current: Rx = 16 mA, 100nA register retention
Programmable Pout: -18 to +17 dBm in 1dB steps
Constant RF performance over voltage range of chip
FSK Bit rates up to 300 kb/s
Fully integrated synthesizer with a resolution of 61 Hz
FSK, GFSK, MSK, GMSK and OOK modulations
Built-in Bit Synchronizer performing Clock Recovery
Incoming Sync Word Recognition
115 dB+ Dynamic Range RSSI
Automatic RF Sense with ultra-fast AFC
Packet engine with CRC, AES-128 encryption and 66-
byte FIFO
Built-in temperature sensor and Low Battery indicator
QFN 24 Package - Operating Range [-40;+85°C]
Pb-free, Halogen free, RoHS/WEEE compliant product
Part Number
Oscillator
RC
AFC
RESET
SPI
RXTX
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
Tape & Reel
Delivery
DATASHEET
www.semtech.com
MOQ / Multiple
SX1231
3000 pieces

SX1231-31SKB915 Summary of contents

Page 1

... SX1231 Transceiver Low Power Integrated UHF Transceiver PA_BOOST GENERAL DESCRIPTION The SX1231 is a highly integrated RF transceiver capable of operation over a wide frequency range, including the 433, 868 and 915 MHz license-free ISM (Industry Scientific and Medical) frequency bands. Its highly integrated architecture allows for a minimum of external components whilst maintaining maximum design flexibility ...

Page 2

... Over Current Protection ........................................................................................................................... 21 3.5. Receiver Description ..................................................................................................................................... 22 3.5.1. Block Diagram .......................................................................................................................................... 22 3.5.2. LNA - Single to Differential Buffer ............................................................................................................ 22 3.5.3. Automatic Gain Control ............................................................................................................................ 23 3.5.4. Quadrature Mixer - ADCs - Decimators.................................................................................................... 24 3.5.5. Channel Filter ........................................................................................................................................... 25 3.5.6. DC Cancellation ....................................................................................................................................... 26 3.5.7. Complex Filter - OOK ............................................................................................................................... 26 3.5.8. RSSI ......................................................................................................................................................... 26 Rev 3 - April 2010 Page 2 SX1231 DATASHEET Page www.semtech.com ...

Page 3

... Control ...................................................................................................................................................... 45 5.3. Digital IO Pins Mapping................................................................................................................................. 45 5.3.1. DIO Pins Mapping in Continuous Mode ................................................................................................... 46 5.3.2. DIO Pins Mapping in Packet Mode .......................................................................................................... 46 5.4. Continuous Mode .......................................................................................................................................... 47 5.4.1. General Description.................................................................................................................................. 47 5.4.2. Tx Processing........................................................................................................................................... 47 5.4.3. Rx Processing .......................................................................................................................................... 48 5.5. Packet Mode ................................................................................................................................................. 48 5.5.1. General Description.................................................................................................................................. 48 Rev 3 - April 2010 Page 3 SX1231 DATASHEET www.semtech.com ...

Page 4

... Chip Revisions ...................................................................................................................................................... 78 9.1. RC Oscillator Calibration............................................................................................................................... 78 9.2. Listen Mode................................................................................................................................................... 78 9.2.1. Resolutions............................................................................................................................................... 78 9.2.2. Exiting Listen Mode .................................................................................................................................. 79 9.3. OOK Floor Threshold Default Setting ........................................................................................................... 79 9.4. OCP Block..................................................................................................................................................... 79 9.5. AFC Control .................................................................................................................................................. 79 9.5.1. AfcAutoClearOn ....................................................................................................................................... 79 9.5.2. LowBetaAfcOn and LowBetaAfcOffset..................................................................................................... 79 10. Revision History .................................................................................................................................................... 80 Rev 3 - April 2010 Page 4 SX1231 DATASHEET www.semtech.com ...

Page 5

... Figure 19. Listen Mode Sequence (no wanted signal is received) .............................................................................. 37 Figure 20. Listen Mode Sequence (wanted signal is received) ................................................................................... 39 Figure 21. Auto Modes of Packet Handler ................................................................................................................... 40 Figure 22. SX1231 Data Processing Conceptual View ............................................................................................... 41 Figure 23. SPI Timing Diagram (single access) .......................................................................................................... 42 Figure 24. FIFO and Shift Register (SR) ..................................................................................................................... 43 Figure 25. FifoLevel IRQ Source Behavior .................................................................................................................. 44 Figure 26 ...

Page 6

... ADVANCED COMMUNICATIONS & SENSING Figure 42. Recommended Land Pattern ..................................................................................................................... 76 Figure 43. Tape & Reel Specification .......................................................................................................................... 77 Figure 44. Listen Mode Resolutions, V2a ................................................................................................................... 78 Figure 45. Listen Mode Resolution, V2b ..................................................................................................................... 78 Figure 46. Exiting Listen Mode in SX1231 V2a ........................................................................................................... 79 Figure 47. RegTestOok Description ............................................................................................................................ 79 Index of Tables Table 1. SX1231 Pinouts .............................................................................................................................................. 10 Table 2. Absolute Maximum Ratings ............................................................................................................................ 11 Table 3. Operating Range ............................................................................................................................................ 11 Table 4 ...

Page 7

... Phase-Locked Loop POR Power On Reset RBW Resolution BandWidth RF Radio Frequency RSSI Received Signal Strength Indicator Rx Receiver SAW Surface Acoustic Wave SPI Serial Peripheral Interface SR Shift Register Stby Standby Tx Transmitter uC Microcontroller VCO Voltage Controlled Oscillator XO Crystal Oscillator XOR eXclusive OR Page 7 SX1231 DATASHEET www.semtech.com ...

Page 8

... SX1231 include a 66 byte TX/RX FIFO, configurable automatic packet handler, listen mode, temperature sensor and configurable DIOs which greatly enhance system flexibility whilst at the same time significantly reducing MCU requirements. The SX1231 complies with both ETSI and FCC regulatory requirements and is available QFN 24 lead package 1.1. Simplified Block Diagram VBAT1& ...

Page 9

... Pin and Marking Diagram The following diagram shows the pin arrangement of the QFN package, top view. Notes yyww refers to the date code xxxxxx refers to the lot number Rev 3 - April 2010 Figure 2. Pin Diagram Figure 3. Marking Diagram Page 9 SX1231 DATASHEET www.semtech.com ...

Page 10

... ADVANCED COMMUNICATIONS & SENSING 1.3. Pin Description Table 1 SX1231 Pinouts Number 0 GROUND 1 2 VR_ANA 3 VR_DIG DIO1/DCLK 9 DIO2/DATA PA_BOOST 24 Note PA_BOOST can be left floating if unused Rev 3 - April 2010 Name Type - Exposed ground pad - VBAT1 Supply voltage - Regulated supply voltage for analogue circuitry ...

Page 11

... ADVANCED COMMUNICATIONS & SENSING 2. Electrical Characteristics 2.1. ESD Notice The SX1231 is a high performance radio frequency device. It satisfies: Class 2 of the JEDEC standard JESD22-A114-B (Human Body Model) on all pins. Class B of the JEDEC standard JESD22-A115-A (Machine Model) on all pins. Class IV of the JEDEC standard JESD22-C101C (Charged Device Model) on pins 2-3-21-23-24, Class III on all other pins ...

Page 12

... RFIO pin RFOP = -1 dBm, on RFIO pin Conditions Programmable See section 7.1 From Standby mode 200 kHz step 1 MHz step 5 MHz step 7 MHz step 12 MHz step 20 MHz step 25 MHz step 19 FSTEP = FXOSC/2 Page 12 SX1231 DATASHEET Min Typ Max Unit - 0 1 1.25 1.5 ...

Page 13

... Offset = +/- 2 MHz Offset = +/- 10 MHz Offset = +/- 1 MHz Offset = +/- 2 MHz Offset = +/- 10 MHz Offset = +/- 1 MHz Offset = +/- 2 MHz Offset = +/- 10 MHz Lowest LNA gain Highest LNA gain Lowest LNA gain Highest LNA gain Programmable Page 13 SX1231 DATASHEET - 62.5 - kHz 1.2 - 300 kbps 1.2 - 32.768 kbps 0.6 ...

Page 14

... Programmable with 1dB steps Max Min With external match to 50 ohms From VDD=1.8V to 3.6V 50 kHz Offset from carrier 868 / 915 MHz bands 434 / 315 MHz bands BT=0.5 . Measurement conditions as defined by EN 300 220-1 V2.1.1 Frequency Synthesizer enabled, PaRamp = 10 us 4.8 kb/s. Page 14 SX1231 DATASHEET 1 ...

Page 15

... Conditions Imax = 1 mA Imax = -1 mA from MOSI change to SCK rising edge from SCK rising edge to MOSI change from NSS falling edge to SCK rising edge from SCK falling edge to NSS rising edge, normal mode Page 15 SX1231 DATASHEET Min Typ Max Unit 0 VDD - - ...

Page 16

... Reference Oscillator The crystal oscillator is the main timing reference of the SX1231 used as a reference for the frequency synthesizer and as a clock for the digital processing. The XO startup time, TS_OSC, depends on the actual XTAL being connected on pins XTA and XTB. When using the built- in sequencer, the SX1231 optimizes the startup time and automatically triggers the PLL when the XO signal is stable ...

Page 17

... The VCO calibration is fully automated. A coarse adjustment is carried out at power on reset, and a fine tuning is performed each time the SX1231 PLL is activated. Automatic calibration times are fully transparent to the end-user, as their processing time is included in the TS_TE and TS_RE specifications. 3.3.3.2. PLL Bandwidth ...

Page 18

... PLL lock time TS_FS is a function of a number of technical factors, such as synthesized frequency, frequency step, etc. When using the built-in sequencer, the SX1231 optimizes the startup time and automatically starts the receiver or the transmitter when the PLL has locked. To manually control the startup time, the user should either wait for TS_FS max given in the specification, or monitor the signal PLL lock detect indicator, which is set when the PLL has is within its locking range ...

Page 19

... Architecture Description 3.4.2. Bit Rate Setting When using the SX1231 in Continuous mode, the data stream to be transmitted can be input directly to the modulator via pin 9 (DIO2/DATA asynchronous manner, unless Gaussian filtering is used, in which case the DCLK signal on pin 10 (DIO1/DCLK) is used to synchronize the data stream. See section 3.4.5 for details on the Gaussian filter. ...

Page 20

... Fdev DEV STEP BR ≤ ------ - + 500kHz F 2 DEV Page 20 SX1231 DATASHEET Actual BR OOK (b/s) 1.2 kbps 1200.015 2.4 kbps 2400.060 4.8 kbps 4799.760 9.6 kbps 9600.960 19.2 kbps 19196.16 38415.36 76738.60 153846.1 57553.95 115107.9 12.5 kbps 12500 ...

Page 21

... PaRamp setting is changed, in order to recalibrate the built-in filter. 3.4.6. Power Amplifiers Three power amplifier blocks are embedded in the SX1231. The first one, herein referred to as PA0, can generate up to +13 dBm into a 50 Ohm load. PA0 shares a common front-end pin RFIO (pin 21) with the receiver LNA. ...

Page 22

... ADVANCED COMMUNICATIONS & SENSING 3.5. Receiver Description The SX1231 features a digital receiver with the analog to digital conversion process being performed directly following the LNA-Mixers block. The zero-IF receiver is able to handle (G)FSK and (G)MSK modulation. ASK and OOK modulation is, however, demodulated by a low-IF architecture. All the filtering, demodulation, gain control, synchronization and packet handling is performed digitally, which allows a very wide range of bit rates and frequency deviations to be selected ...

Page 23

... Lower Linearity Lower Noise Figure The following table summarizes the performance (typical figures) of the complete receiver: Rev 3 - April 2010 7dB 11dB Figure 7. AGC Thresholds Settings Page 23 SX1231 DATASHEET Pin [dBm] 9dB 11dB G5 G6 Lower Sensitivity Higher Linearity Higher Noise Figure www.semtech.com ...

Page 24

... AFC and the AGC is RxBwAfc instead of the standard RxBw setting. This may impact the sensitivity of the receiver, and the setting of RssiThreshold accordingly 3.5.3.2. AGC Reference The AGC reference level is automatically computed in the SX1231, according to: AGC Reference [dBm] = -174 + NF + DemodSnr +10.log(2*RxBw) + FadingMargin [dBm] With 7dB : LNA’ ...

Page 25

... ADVANCED COMMUNICATIONS & SENSING 3.5.5. Channel Filter The role of the channel filter is to filter out the noise and interferers outside of the channel. Channel filtering on the SX1231 is implemented with a 16-tap Finite Impulse Response (FIR) filter, providing an outstanding Adjacent Channel Rejection performance, even for narrowband applications. ...

Page 26

... DCC setting while monitoring the receiver sensitivity. 3.5.7. Complex Filter - OOK In OOK mode the SX1231 is modified to a low-IF architecture. The IF frequency is automatically set to half the single side bandwidth of the channel filter (F = 0.5 x RxBw). The Local Oscillator is automatically offset by the IF in the OOK receiver. ...

Page 27

... ADVANCED COMMUNICATIONS & SENSING 3.5.10. FSK Demodulator The FSK demodulator of the SX1231 is designed to demodulate FSK, GFSK, MSK and GMSK modulated signals most efficient when the modulation index of the signal is greater than 0.5 and below 10: The output of the FSK demodulator can be fed to the Bit Synchronizer (described in section 3.5.12), to provide the companion processor with a synchronous data stream in Continuous mode ...

Page 28

... Fixed Threshold: The value is selected through OokFixedThresh Average Threshold: Data supplied by the RSSI block is averaged, and this operation mode should only be used with DC-free encoded data. Rev 3 - April 2010 Set SX1231 in OOK Rx mode Adjust Bit Rate, Channel filter BW Default OokFixedThresh setting No input signal ...

Page 29

... The bit rate matching between the transmitter and the receiver must be better than 6.5 %. Notes - If the Bit Rates of transmitter and receiver are known to be the same, the SX1231 will be able to receive an infinite unbalanced sequence (all “0s” or all ”1s”) with no restriction. ...

Page 30

... Upon user request, by setting bit AfcStart in RegAfcFei, if AfcAutoOn = 0 Rev 3 - April 2010 ⎛ ⎞ BR × ------ - = ⎝ ⎠ DEV 2 × = FEI F FeiValue STEP SX1231 in Rx mode Preamble-modulated input signal Signal level > Sensitivity Set FeiStart = 1 No FeiDone = 1 Yes Read FeiValue Figure 12. FEI Process Page 30 SX1231 DATASHEET www.semtech.com ...

Page 31

... Ageing compensation is a good example. The SX1231 offers an alternate receiver bandwidth setting during the AFC phase, to accommodate large LO drifts. If the user considers that the received signal may be out of the receiver bandwidth, a higher channel filter bandwidth can be programmed in RegAfcBw, at the expense of the receiver noise floor, which will impact upon sensitivity ...

Page 32

... TempValue(t) TempValue(t)-1 Returns 150d (typ.) Needs calibration It takes less than 100 microseconds for the SX1231 to evaluate the temperature (from setting TempMeasStart TempMeasRunning reset). 3.5.17. Timeout Function The SX1231 includes a Timeout function, which allows it to automatically shut-down the receiver after a receive sequence and therefore save energy ...

Page 33

... By default, when switching from one operating mode to another, the circuit takes care of the sequence of events in such a way that the transition timing is optimized. For example, when switching from Sleep mode to Transmit mode, the SX1231 goes first to Standby mode (XO started), then to frequency synthesizer mode, and finally, when the PLL has locked, to transmit mode ...

Page 34

... TxStartCondition is fulfilled. 4.2.3. Receiver Startup Time It is highly recommended to use the built-in sequencer of the SX1231, to optimize the delays when setting the chip in receive mode. It guarantees the shortest startup times, hence the lowest possible energy usage, for battery operated systems ...

Page 35

... Tcf = 21 / (4.RxBw) Tcf = 34 / (4.RxBw) Tdcc = max(8 , 2^(round(log2(8.RxBw.Tbit)+1)) / (4.RxBw) Tpllafc = 5 / PLLBW (PLLBW = 300 kHz) (also denoted TS_AFC in the general specification) Tafc = 4 x Tbit Trssi = 2 x int(4.RxBw.Tbit)/(4.RxBw) Page 35 SX1231 DATASHEET RSSI Reception of Packet sampling Trssi The LNA gain is adjusted by the AGC, according to the RSSI result DC Cutoff’ ...

Page 36

... Respect the Tx start procedure, described in section 4.2.2 Receiver hop from (0) SX1231 mode (1) Change the carrier frequency in the RegFrf registers Program the SX1231 in FS mode (2) Program the SX1231 in FS mode (3) Turn the transceiver back to Rx mode (4) Respect the Rx start procedure, described in section 4.2.4 Note all sequences described above are assuming that the sequencer is turned on (SequencerOff=0 in RegOpMode) ...

Page 37

... ADVANCED COMMUNICATIONS & SENSING 4.3. Listen mode The circuit can be set to Listen mode, by setting ListenOn in RegOpMode this mode, SX1231 spends most of the time in Idle mode, during which only the RC oscillator runs. Periodically the receiver is woken up and listens for an RF signal wanted signal is detected, the receiver is kept on and the data is demodulated. ...

Page 38

... Mode. Listen mode stops and must be disabled. Chip stays in Rx mode until PayloadReady or Timeout interrupt occurs. Listen mode then 10 resumes in Idle state. FIFO content is lost at next Rx wakeup. Rev 3 - April 2010 Input Signal Power SyncAddressMatch >= RssiThreshold Required Not Required Required Required Description Page 38 SX1231 DATASHEET www.semtech.com ...

Page 39

... For applications enduring large temperature variations, and for which the power supply is never removed, RC calibration can be performed upon user request. RcCalStart in RegOsc1 can be used to trigger this calibration, and the flag RcCalDone will be set automatically when the calibration is over. Rev 3 - April 2010 Idle Rx Idle Rx Idle Rx Page 39 SX1231 DATASHEET Mode Idle Rx www.semtech.com ...

Page 40

... Automatic reception (AutoRx) : Mode = Rx, IntermediateMode = Sleep, EnterCondition = CrcOk, ExitCondition = falling edge of FifoNotEmpty Automatic reception of acknowledge (AutoRxAck): Mode = Tx, IntermediateMode = Rx, EnterCondition = PacketSent, ExitCondition = CrcOk ... Rev 3 - April 2010 Intermediate State defined by IntermediateMode EnterCondition Final state defined By Mode in RegOpMode Figure 21. Auto Modes of Packet Handler Page 40 SX1231 DATASHEET ExitCondition www.semtech.com ...

Page 41

... Overview 5.1.1. Block Diagram Figure below illustrates the SX1231 data processing circuit. Its role is to interface the data to/from the modulator/ demodulator and the uC access points (SPI and DIO pins). It also controls all the configuration registers. The circuit contains several control blocks which are described in the following paragraphs. ...

Page 42

... In FIFO mode, if the address was the FIFO address then the bytes will be written / read at the FIFO address. In Burst mode, if the address was not the FIFO address, then it is automatically incremented at each new byte received. Rev 3 - April 2010 Page 42 SX1231 DATASHEET www.semtech.com ...

Page 43

... PacketSent: PacketSent interrupt source goes high when the SR's last bit has been sent. FifoLevel: Threshold can be programmed by FifoThreshold in RegFifoThresh. Its behavior is illustrated in figure below. Rev 3 - April 2010 byte1 byte0 8 Data Tx/Rx SR (8bits) 1 MSB Figure 24. FIFO and Shift Register (SR) Page 43 SX1231 DATASHEET FIFO LSB www.semtech.com ...

Page 44

... Figure 25. FifoLevel IRQ Source Behavior FIFO status Not cleared Not cleared Not cleared To allow the user to write the FIFO in Stdby/Sleep before Tx Cleared Cleared Not cleared To allow the user to read FIFO in Stdby/Sleep mode after Rx Cleared Page 44 SX1231 DATASHEET # of bytes in FIFO Comments www.semtech.com ...

Page 45

... The control block configures and controls the full chip's behavior according to the settings programmed in the configuration registers. 5.3. Digital IO Pins Mapping Six general purpose IO pins are available on the SX1231, and their configuration in Continuous or Packet mode is controlled through RegDioMapping1 and RegDioMapping2. Rev 3 - April 2010 ...

Page 46

... PllLock AutoMode Timeout FifoFull FifoNotEmpty Rssi Rssi Data RxReady SyncAddress LowBat PllLock PllLock AutoMode ModeReady FifoFull FifoNotEmpty TxReady TxReady Data LowBat LowBat LowBat PllLock PllLock AutoMode Page 46 SX1231 DATASHEET DIO1 DIO0 - - - - LowBat LowBat - ModeReady - - - - LowBat LowBat - ModeReady - PllLock - - LowBat LowBat PllLock ...

Page 47

... DCLK Note the use of DCLK is required when the modulation shaping is enabled (see section 3.4.5). Rev 3 - April 2010 CONTROL Figure 27. Continuous Mode Conceptual View T_DATA T_DATA Figure 28. Tx Processing in Continuous Mode Page 47 SX1231 DATASHEET DIO0 DIO1/DCLK DIO2/DATA DIO3 DIO4 DIO5 SPI NSS ...

Page 48

... In Packet mode the NRZ data to (from) the (de)modulator is not directly accessed by the uC but stored in the FIFO and accessed via the SPI interface. In addition, the SX1231 packet handler performs several packet oriented tasks such as Preamble and Sync word generation, CRC calculation/check, whitening/dewhitening of data, Manchester encoding/decoding, address filtering, AES encryption/decryption, etc ...

Page 49

... Preamble (1010...) Sync word (Network ID) Optional Address byte (Node ID) Message data Optional 2-bytes CRC checksum Rev 3 - April 2010 CONTROL PACKET FIFO HANDLER (+SR) Figure 30. Packet Mode Conceptual View Page 49 SX1231 DATASHEET DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 SPI NSS SCK MOSI MISO ...

Page 50

... Up to 255 bytes Payload (min 1 byte) Figure 31. Fixed Length Packet Format DC free Data encoding CRC checksum calculation AES Enc/Dec Length Address byte byte Up to 255 bytes Payload (min 2 bytes) Figure 32. Variable Length Packet Format Page 50 SX1231 DATASHEET CRC 2-bytes Message CRC 2-bytes www.semtech.com ...

Page 51

... Optional DC-free encoding of the data (Manchester or whitening) Only the payload (including optional address and length fields) is required to be provided by the user in the FIFO. Rev 3 - April 2010 DC free Data encoding Address Message byte unlimited length Payload Figure 33. Unlimited Length Packet Format Page 51 SX1231 DATASHEET www.semtech.com ...

Page 52

... AES is the symmetric-key block cipher that provides the cryptographic capabilities to the transceiver. The system proposed can work with 128-bit long fixed keys. The fixed key is stored in a 16-byte write only user configuration register, which retains its value in Sleep mode. Rev 3 - April 2010 Page 52 SX1231 DATASHEET www.semtech.com ...

Page 53

... If the address filtering is expected then AddressFiltering must be enabled on the transmitter side as well to prevent address byte to be encrypted. Crc check being performed on encrypted data, CrcOk interrupt will occur "decryption time" before PayloadReady interrupt. Rev 3 - April 2010 Page 53 SX1231 DATASHEET www.semtech.com ...

Page 54

... AES encryption is not feasible on large packets, since all Payload bytes need the FIFO at the same time to perform encryption 5.5.7. Packet Filtering SX1231's packet handler offers several mechanisms for packet filtering, ensuring that only useful packets are made available to the uC, reducing significantly system power consumption and software complexity. 5.5.7.1. Sync Word Based Sync word filtering/recognition is used for identifying the start of the payload and also for network identification ...

Page 55

... Please note that in both cases, the two CRC checksum bytes are stripped off by the packet handler and only the payload is made available in the FIFO. The CRC is based on the CCITT polynomial as shown below. This implementation also detects errors due to leading and trailing zeros. Rev 3 - April 2010 Page 55 SX1231 DATASHEET www.semtech.com ...

Page 56

... Manchester encoding/decoding is thus made transparent for the user, who still provides/retrieves NRZ data to/from the FIFO. 1/BR RF chips @ BR ... 1 1 User/NRZ bits ... 1 1 Manchester OFF User/NRZ bits ... 1 1 Manchester ON Rev 3 - April 2010 16 CRC Polynomial = Figure 34. CRC Implementation 1/BR ...Sync Figure 35. Manchester Encoding/Decoding Page 56 SX1231 DATASHEET Payload... www.semtech.com 0 ... t ... ... ...

Page 57

... CRC checksum is then XORed with this random sequence as shown below. The data is de-whitened on the receiver side by XORing with the same random sequence. Payload whitening/de-whitening is thus made transparent for the user, who still provides/retrieves NRZ data to/from the FIFO Rev 3 - April 2010 ran ata Figure 36. Data Whitening Page 57 SX1231 DATASHEET hite ata www.semtech.com X 0 ...

Page 58

... Semtech ID relating the silicon revision 0x9F PA selection and Output Power control 0x09 Control of the PA ramp time in FSK mode 0x1A Over Current Protection control 0x40 - 0xB0 - 0x7B - 0x9B - 0x08 0x88 LNA settings 0x86 0x55 Channel Filter BW Control Page 58 SX1231 DATASHEET Description www.semtech.com ...

Page 59

... Sync Word Recognition control 0x00 0x01 Sync Word bytes, 1 through 8 0x10 Packet mode settings 0x40 Payload length setting 0x00 Node address 0x00 Broadcast address 0x00 Auto modes settings 0x0F 0x8F Fifo threshold, Tx start condition 0x02 Packet mode settings Page 59 SX1231 DATASHEET Description www.semtech.com ...

Page 60

... Registers for which the Default value differs from the Reset value are denoted the tables of section 6 Rev 3 - April 2010 Default Reset (recom (built-in) mended) 0x00 16 bytes of the cypher key 0x01 Temperature Sensor control 0x00 Temperature readout 0x1B Sensitivity boost 0x00 AFC offset for low modulation index AFC - Internal test registers Page 60 SX1231 DATASHEET Description www.semtech.com ...

Page 61

... Data shaping: in FSK shaping 01 Gaussian filter 1.0 10 Gaussian filter 0.5 11 Gaussian filter 0.3 in OOK shaping 01 filtering with f cutoff 10 filtering with f cutoff 11 reserved rw 0x1a MSB of Bit Rate (Chip Rate when Manchester encoding is enabled) Page 61 SX1231 DATASHEET = BR = 2*BR www.semtech.com ...

Page 62

... Real-time (not latched) output of the Low Battery detector, when enabled Low Battery detector enable signal 0 LowBat off 1 LowBat on rw 010 Trimming of the LowBat threshold: 000 1.695 V 001 1.764 V 010 1.835 V 011 1.905 V 100 1.976 V 101 2.045 V 110 2.116 V 111 2.185 V Page 62 SX1231 DATASHEET FXOSC ---------------------------------- - = BitRate www.semtech.com ...

Page 63

... Duration of the Rx phase in Listen mode (startup time included, see section 4.2. ListenCoef ListenRx r 0x22 Version code of the chip. Bits 7-4 give the full revision number; bits 3-0 give the metal mask revision number. Page 63 SX1231 DATASHEET ⋅ Re Idle Listen solIdle ⋅ Listen solRx www ...

Page 64

... Enables overload current protection (OCP) for the PA: 0 OCP disabled 1 OCP enabled rw 1010 Trimming of OCP current: × OcpTrim Imax 95 mA OCP by default Page 64 SX1231 DATASHEET ( ) mA www.semtech.com ...

Page 65

... RxBw RxBwMant 2 See Table 13 for tabulated values rw 100 DccFreq parameter used during the AFC rw 01 RxBwMant parameter used during the AFC rw 011 * RxBwExp parameter used during the AFC Page 65 SX1231 DATASHEET × 4 RxBw ----------------------------------------- - + 2 DccFreq 2 π 2 × 10 RxBwMant = 24 11 reserved FXOSC ...

Page 66

... RSSI is on-going 1 RSSI sampling is finished, result available w 0 Trigger a RSSI measurement when set. Always reads 0. r 0xFF Absolute value of the RSSI in dBm, 0.5dB steps. RSSI = - RssiValue/2 [dBm] Page 66 SX1231 DATASHEET average reserved 1.0 dB 2.0 dB 4.0 dB 6.0 dB 001 once every 2 chips 011 ...

Page 67

... Please note that in Sleep mode a small delay can be observed between AutoMode interrupt and the corresponding enter/exit condition. r/rwc 0 Set when Sync and Address (if enabled) are detected. Cleared when leaving Rx or FIFO is emptied. This bit is read only in Packet mode, rwc in Continuous mode Page 67 SX1231 DATASHEET www.semtech.com ...

Page 68

... Timeout interrupt is generated TimeoutRxStart *16*T after switching to Rx mode if Rssi interrupt doesn’t occur (i.e. RssiValue > RssiThreshold) 0x00: TimeoutRxStart is disabled rw 0x00 Timeout interrupt is generated TimeoutRssiThresh *16*T after Rssi interrupt if PayloadReady interrupt doesn’t occur. 0x00: TimeoutRssiThresh is disabled Page 68 SX1231 DATASHEET bit bit www.semtech.com ...

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... Used if SyncOn is set and (SyncSize +1) > 0x01 th 6 byte of Sync word. * Used if SyncOn is set and (SyncSize +1) > 0x01 th 7 byte of Sync word. * Used if SyncOn is set and (SyncSize +1) > 0x01 th 8 byte of Sync word. * Used if SyncOn is set and (SyncSize + Page 69 SX1231 DATASHEET www.semtech.com ...

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... Rising edge of CrcOk or Timeout 100 Rising edge of PayloadReady or Timeout 101 Rising edge of SyncAddress or Timeout 110 Rising edge of PacketSent 111 Rising edge of Timeout rw 00 Intermediate mode: 00 Sleep mode (SLEEP) 01 Standby mode (STDBY) 10 Receiver mode (RX) 11 Transmitter mode (TX) Page 70 SX1231 DATASHEET www.semtech.com ...

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... Page 71 SX1231 DATASHEET ) / BitRate otherwise www.semtech.com ...

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... Lsb Needs calibration for accuracy Default Mode Description Value rw 0x1B High sensitivity or normal sensitivity mode: 0x1B Normal mode 0x2D High sensitivity mode rw 0x00 AFC offset set for low modulation index systems, used if AfcLowBetaOn=1 . Offset = LowBetaAfcOffset x 488 Hz Page 72 SX1231 DATASHEET www.semtech.com ...

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... A minimum XTAL frequency of 28 MHz is required to cover the 863-870 MHz band, 29 MHz for the 902-928 MHz band 7.2. Reset of the Chip A power-on reset of the SX1231 is triggered at power up. Additionally, a manual reset can be issued by controlling pin 6. 7.2.1. POR If the application requires the disconnection of VDD from the SX1231, despite of the extremely low Sleep Mode current, the user should wait for 10 ms from of the end of the POR cycle before commencing communications over the SPI bus ...

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... ADVANCED COMMUNICATIONS & SENSING 7.2.2. Manual Reset A manual reset of the SX1231 is possible even for applications in which VDD cannot be physically disconnected. Pin 6 should be pulled high for a hundred microseconds, and then released. The user should then wait for 5 ms before using the chip. ...

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... ADVANCED COMMUNICATIONS & SENSING Note In very cost-sensitive and/or size-constrained applications where it is acceptable to degrade the receiver sensitivity by approximately 2 dB, L5 and C14 can be omitted. Rev 3 - April 2010 Figure 40. +17dBm Schematic Page 75 SX1231 DATASHEET www.semtech.com ...

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... ADVANCED COMMUNICATIONS & SENSING 8. Packaging Information 8.1. Package Outline Drawing The SX1231 is available in a 24-lead QFN package as show in Figure 41. NOTES: 8.2. Recommended Land Pattern Rev 3 - April 2010 PIN 1 INDICATOR (LASER MARK SEATING PLANE aaa LxN E bxN e/2 bbb e D/2 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). ...

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... The thermal impedance of this package is: Theta ja = 29° C/W typ., calculated from a package in still air 4-layer FR4 PCB, as per the Jedec standard. 8.4. Tape & Reel Specification Note Single Sprocket holes Rev 3 - April 2010 Figure 43. Tape & Reel Specification Page 77 SX1231 DATASHEET www.semtech.com ...

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... This is not required in the version V2b any more, where the calibration is fully automatic. 9.2. Listen Mode 9.2.1. Resolutions On the SX1231 V2a, the Listen mode resolutions were identical for the Idle phase and the Rx phase. They are now independently configurable, adding flexibility in the setup of the Listen mode. Rev 3 - April 2010 ...

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... AFC Control The following differences are observed between silicon revisions V2a and V2b: 9.5.1. AfcAutoClearOn On the SX1231 V2a required to manually clear AfcValue in RegAfcFei, when the device mode. AfcAutoClear function is fully functional on the silicon version V2b. 9.5.2. LowBetaAfcOn and LowBetaAfcOffset Those two bits enable a functionality that was not available on the silicon version V2a. ...

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... Describe handling method for Packets larger than the FIFO size Document AFC for low modulation index, timing diagrams, adjust Tana Correct OCP default configuration Document RegTestAfc at address 0x71 Add section describing setup for low modulation index systems Add application schematics Rev 3 - April 2010 Comment Page 80 SX1231 DATASHEET www.semtech.com ...

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... Contact information Advanced Communication and Sensing Products Division Phone: (805) 498-2111 Fax: (805) 498-3804 Rev 3 - April 2010 Semtech Corporation 200 Flynn Road, Camarillo, CA 93012 E-mail: sales@semtech.com acsupport@semtech.com Internet: http://www.semtech.com Page 81 SX1231 DATASHEET www.semtech.com ...

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