DP83865DVH National Semiconductor, DP83865DVH Datasheet
DP83865DVH
Specifications of DP83865DVH
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DP83865DVH Summary of contents
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... TX and 1000BASE-T specifications SYSTEM DIAGRAM MII GMII RGMII DP83820 10/100/1000 Mb/s ETHERNET MAC PHYTER® registered trademark of National Semiconductor Corporation © 2004 National Semiconductor Corporation ® V Integrated PMD sublayer featuring adaptive equalization and baseline wander compensation according to ANSI X3.T12 3 2.5 V MAC interfaces: IEEE 802 ...
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Block Diagram MGMT INTERFACE C MGMT & PHY CNTRL 100BASE-TX 10BASE-T Block MII 100BASE-TX PCS 100BASE-TX PMA 100BASE-TX PMD MLT-3 100 Mb/s www.national.com COMBINED MII / GMII / RGMII INTERFACE MII 1000BASE-T Block Block MII 1000BASE-T 10BASE-T PLS 1000BASE-T 10BASE-T ...
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Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 MAC Interfaces (MII, ...
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... TMS 27 TDO 28 IO_VDD 29 VSS 30 TDI 31 TRST 32 RESET 33 VDD_SEL_STRAP 34 CORE_VDD 35 VSS 36 IO_VDD 37 VSS 38 www.national.com DP83865DVH Gig PHYTER V Figure 1. DP83865 Pinout Order Part Number: DP83865DVH 4 102 BG_REF 101 2V5_AVDD1 100 1V8_AVDD3 99 VSS 98 1V8_AVDD2 97 VSS 96 2V5_AVDD2 95 PHYADDR4_STRAP 94 MULTI_EN_STRAP / TX_TRIGGER 93 VSS 92 CORE_VDD 91 VSS 90 IO_VDD 89 MDIX_EN_STRAP ...
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Pin Description The DP83865 pins are classified into the following interface categories (each is described in the sections that follow): — MAC Interfaces — Management Interface — Media Dependent Interface — JTAG Interface — Clock Interface — Device Configuration ...
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Pin Description (Continued) PQFP Signal Name Type Pin # TXD0/TX0 I TXD1/TX1 TXD2/TX2 TXD3/TX3 TXD4 TXD5 TXD6 TXD7 TX_EN/TXEN_ER I GTX_CLK/TCK I TX_ER I RX_CLK O_Z RXD0/RX0 O_Z RXD1/RX1 RXD2/RX2 RXD3/RX3 RXD4 RXD5 RXD6 RXD7 RX_ER/RXDV_ER O_Z RX_DV/RCK O_Z ...
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Pin Description (Continued) 1.2 Management Interface PQFP Signal Name Type Pin # MDC I 81 MDIO I/O 80 INTERRUPT O_Z 1.3 Media Dependent Interface PQFP Signal Name Type PIn # MDIA_P I/O 108 MDIA_N 109 MDIB_P 114 ...
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Pin Description (Continued) PQFP Signal Name Type PIn # TCK I 1.5 Clock Interface PQFP Signal Name Type Pin # CLK_IN I CLK_OUT O CLK_TO_MAC O 1.6 Device Configuration and LED Interface (See section “3.7 PHY Address, Strapping Options ...
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Pin Description (Continued) PQFP Signal Name Type Pin # ACTIVITY_LED / I/O, 7 SPEED0_STRAP S, PD LINK10_LED /RLED/ I/O, 8 SPEED1_STRAP S, PD LINK100_LED / I/O, 9 DUPLEX_STRAP S, PU LINK1000_LED / I/O, 10 AN_EN_STRAP S, PU Description SPEED ...
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Pin Description (Continued) PQFP Signal Name Type Pin # DUPLEX_LED / I/O, PHYADDR0_STRAP S, PU PHYADDR1_STRAP PD PHYADDR2_STRAP PD PHYADDR3_STRAP PD PHYADDR4_STRAP PD MULTI_EN_STRAP / I/O, TX_TRIGGER S, PD MDIX_EN_STRAP I/ MAC_CLK_EN_STRAP TX_SYN_CLK PU ...
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Pin Description (Continued) 1.8 Power and Ground Pins (See section “5.3 Power Supply Decoupling” on page 64.) Signal Name PQFP Pin # IO_VDD 4, 15, 21, 29, 37, 42, 53, 58, 69, 77, 83, 90 CORE_VDD 11, 19, 25, ...
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Pin Description (Continued) 1.10 Pin Assignments in the Pin Number Order Pin # Data Sheet Pin Name 1 NON_IEEE_STRAP 2 RESERVED 3 INTERRUPT 4 IO_VDD 5 VSS 6 TX_TCLK 7 ACTIVITY_LED / SPEED0_STRAP 8 LINK10_LED / RLED/SPEED1_STRAP 9 LINK100_LED ...
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Pin Description (Continued) Pin # Data Sheet Pin Name 23 RESERVED 24 TCK 25 CORE_VDD 26 VSS 27 TMS 28 TDO 29 IO_VDD 30 VSS 31 TDI 32 TRST 33 RESET 34 VDD_SEL_STRAP 35 CORE_VDD 36 VSS 37 IO_VDD ...
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Pin Description (Continued) Pin # Data Sheet Pin Name 45 RXD7 46 RXD6 47 RXD5 48 CORE_VDD 49 VSS 50 RXD4 51 RXD3/RX3 52 RXD2/RX2 53 IO_VDD 54 VSS 55 RXD1/RX1 56 RXD0/RX0 www.national.com Table 1. Type Connection / ...
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Pin Description (Continued) Pin # Data Sheet Pin Name 57 RX_CLK 58 IO_VDD 59 VSS 60 TX_CLK/RGMII_SEL1 61 TX_ER 62 TX_EN/TXEN_ER 63 CORE_VDD 64 VSS 65 TXD7 66 TXD6 67 TXD5 68 TXD4 69 IO_VDD 70 VSS 71 TXD3/TX3 ...
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Pin Description (Continued) Pin # Data Sheet Pin Name 79 GTX_CLK/TCK 80 MDIO 81 MDC 82 VSS 83 IO_VDD 84 RESERVED 85 CLK_TO_MAC 86 CLK_IN 87 CLK_OUT 88 MAC_CLK_EN_STRAP 89 MDIX_EN_STRAP 90 IO_VDD 91 VSS 92 CORE_VDD 93 VSS ...
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Pin Description (Continued) Pin # Data Sheet Pin Name 107 VSS 108 MDIA_P 109 MDIA_N 110 VSS 111 RX_VDD 112 VSS 113 VSS 114 MDIB_P 115 MDIB_N 116 VSS 117 RX_VDD 118 VSS 119 VSS 120 MDIC_P 121 MDIC_N ...
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Register Block 2.1 Register Definitions Register maps and address definitions are given in the following table: Table 2. Register Block - DP83865 Register Map Offset Access Hex Decimal 0x00 0 RW 0x01 1 RO 0x02 2 RO 0x03 3 ...
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Register Block (Continued) 19 www.national.com ...
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Register Block (Continued) www.national.com 20 ...
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Register Block (Continued) 2.3 Register Description In the register description under the ‘Default’ heading, the following definitions hold true: — Read Write access — Read Only access — Latched High until read, based ...
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Register Block (Continued) Table 3. Basic Mode Control Register (BMCR) address 0x00 Bit Bit Name 11 Power_Down 10 Isolate 9 Restart_AN 8 Duplex 7 Collision Test 6 Speed[1] 5:0 Reserved Table 4. Basic Mode Status Register (BMSR) address 0x01 ...
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Register Block (Continued) Table 4. Basic Mode Status Register (BMSR) address 0x01 12 10BASE-T Full Duplex 11 10BASE-T Half Duplex 10 100BASE-T2 Full Duplex 9 100BASE-T2 Half Duplex 8 1000BASE-T Extended Status 7 Reserved 6 Preamble Suppression 5 Auto-Negotiation ...
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Register Block (Continued) Table 5. PHY Identifier Register #1 (PHYIDR1) address 0x02 Bit Bit Name 15:0 OUI[3:18] The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83865. The Identifier consists of a con- catenation ...
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Register Block (Continued) Table 7. Auto-Negotiation Advertisement Register (ANAR) address 0x04 Bit Bit Name 8 100BASE-TX Full Duplex 7 100BASE-TX (Half Duplex) 6 10BASE-T Full Duplex 5 10BASE-T (Half Duplex) 4:0 PSB[4:0] This register contains the advertised abilities of ...
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Register Block (Continued) Table 8. Auto-Negotiation Link Partner Ability Register (ANLPAR) address 0x05 Bit Bit Name ACK Reserved 11 ASY_PAUSE 10 PAUSE 9 100BASE-T4 8 100BASE-TX Full Duplex 7 100BASE-TX (Half Duplex) 6 ...
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Register Block (Continued) Table 9. Auto-Negotiate Expansion Register (ANER) address 0x06 Bit Bit Name 15:5 Reserved 4 PDF 3 LP_NP Able 2 NP Able 1 PAGE_RX 0 LP_AN Able This register contains additional Local Device and Link Partner status ...
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Register Block (Continued) Table 10. Auto-Negotiation Next Page Transmit Register (ANNPTR) address 0x07 Bit Bit Name 11 TOG_TX 10:0 CODE[10:0] This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. Table 11. ...
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Register Block (Continued) Table 11. Auto-Negotiation Next Page Receive Register (ANNPRR) address 0x08 Bit Bit Name 11 TOG_RX 10:0 CODE[10:0] This register contains the next page information sent by its Link Partner during Auto-Negotiation. Table 12. 1000BASE-T Control Register ...
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Register Block (Continued) Table 12. 1000BASE-T Control Register (1KTCR) address 0x09 Bit Bit Name 9 1000BASE-T Full Duplex 8 1000BASE-T Half Duplex 7:0 Reserved Table 13. 1000BASE-T Status Register (1KSTSR) address 0x0A (10’d) Bit Bit Name 15 Master / ...
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Register Block (Continued) Table 14. 1000BASE-T Extended Status Register (1KSCR) address 0x0F (15’d) Bit Bit Name 15 1000BASE-X Full Duplex 14 1000BASE-X Half Duplex 13 1000BASE-T Full Duplex 12 1000BASE-T Half Duplex 11:0 Reserved Table 15. Strap Option Register ...
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Register Block (Continued) Table 16. Link and Auto-Negotiation Status Register (LINK_AN) address 0x11 (17’d) Bit Bit Name 15:12 TP Polarity[3:0] 11 Reserved (Power Down Status) 10 MDIX Status 9 FIFO Error 8 Reserved 7 Shallow Loopback Status 6 Deep ...
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Register Block (Continued) Table 17. Auxiliary Control Register (AUX_CTRL) address 0x12 (18’d) Bit Bit Name 15 Auto-MDIX Enable 14 Manual MDIX Value 13:12 RGMII_EN[1:0] 11:10 Reserved 9 Non-Compliant Mode STRAP[0], RW Non-Compliant Mode Enable: This bit enables the PHY ...
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Register Block (Continued) Table 17. Auxiliary Control Register (AUX_CTRL) address 0x12 (18’d) Bit Bit Name 5 Shallow Deep Loop- back Enable 4 X_Mac 3:1 Reserved 0 Jabber Disable Table 18. LED Control Register (LED_CTRL) address 0x13 (19’d) Bit Bit ...
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Register Block (Continued) Table 18. LED Control Register (LED_CTRL) address 0x13 (19’d) Bit Bit Name 5 reduced LED enable 4 led_on_crc 3 led_on_ie 2 an_fallback_an 1 an_fallback_crc 0 an_fallback_ie Table 19. Interrupt Status Register (INT_STATUS) address 0x14 (20’d) Bit ...
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Register Block (Continued) Table 20. Interrupt Mask Register (INT_MASK) address 0x15 (21’d) Bit Bit Name 15 spd_cng_int_msk 14 lnk_cng_int_msk 13 dplx_cng_int_msk 12 mdix_cng_int_msk 11 pol_cng_int_msk 10 prl_det_flt_int_msk 9 mas_sla_err_int_msk 8 no_hcd_int_msk 7 no_lnk_int_msk 6 jabber_cng_int_msk 5 nxt_pg_rcvd_int_msk 4 an_cmpl_int_msk ...
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Register Block (Continued) Table 22. Interrupt Clear Register (INT_CLEAR) address 0x17 (23’d) Bit Bit Name 15 spd_cng_int_clr 14 lnk_cng_int_clr 13 dplx_cng_int_clr 12 mdix_cng_int_clr 11 pol_cng_int_clr 10 prl_det_flt_int_clr 9 mas_sla_err_int_clr 8 no_hcd_int_clr 7 no_lnk_int_clr 6 jabber_cng_int_clr 5 nxt_pg_rcvd_int_clr 4 an_cmpl_int_clr ...
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Register Block (Continued) Table 24. BIST Configuration Register 1 (BIST_CFG1) address 0x19 (25’d) Bit Bit Name 10 tx_bist_pak_type 9:8 Reserved 7:0 tx_bist_pak Table 25. BIST Configuration Register 2 (BIST_CFG2) address 0x1A (26’d) Bit Bit Name 15 rx_bist_en 14 bist_cnt_sel ...
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Register Block (Continued) Table 28. PHY Support Register #2 (PHY_SUP) address 0x1F (31’d) Bit Bit Name 15:5 Reserved 4:0 PHY Address Default 0, RO Write as 0, ignore on read. STRAP[0_0001], PHY Address: Defines the port on which the ...
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... HDX loopback disable — I/O Voltage Selection — Non-compliant interoperability mode The DP83865 supports six different Ethernet protocols: 10BASE-T Full Duplex and Half Duplex, 100BASE-TX Full Duplex and Half Duplex, 1000BASE-T Full Duplex and Half Duplex. There are three ways to select the speed and duplex modes, i ...
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... Auto-Negotiation All 1000BASE-T PHYs are required to support Auto-Nego- tiation. (The 10/100 Mbps Ethernet PHYs had an option to support Auto-Negotiation, as well as parallel detecting when a link partner did not support Auto-Neg.) The Auto- Negotiation function in 1000BASE-T has three primary pur- poses: — ...
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Configuration (Continued) Table 33. Speed/Duplex Selection, AN_EN = 1 DUP Speed[1] Speed[ 1000/100/10 HDX 1000/100 HDX 1000 HDX 1000/10 HDX 1000/100/10 FDX + HDX ...
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Configuration (Continued) resolved by a random number generation. See IEEE 802.3ab Clause 40.5.1.2 for more details. Table 36. 1000BASE-T Single/Multi-Node, AN_EN = 1 MULTI_EN Forced Mode 0 Single node, Slave priority mode 1 Multi-node, Master priority mode Depending on ...
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Configuration (Continued) 3.4 Auto-Negotiation Register Set The strapping option settings of Auto-Negotiation, speed, and duplex capabilities that initialized during power- reset can be altered any time by writing to the BMCR 0x00, ANAR 0x04 or, to 1KTCR ...
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... ACT 1 1 3.9 Modulate LED on Error The DP83865DVH uses ACT LED to display activity under normal operation. The ACT LED is steady on when there activity. The ACT can also display gigabit idle error and CRC event. To differentiate ACT LED from nor- mal Tx/Rx activity, the rate of the blink is faster when error occurs ...
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Configuration (Continued) 3.10.1 MII/GMII Interface The link speed is determined by Auto-Negotiation, by strapping options register writes. Based on the speed linked, an appropriate MAC interface is enabled. Table 42. Auto-Negotiation Disabled SPEED[1:0] Link Strapped 00 10BASE-T ...
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... BIST functions: Receive BIST and transmit BIST. The receive BIST contains a receive error counter and receive packet counter and the transmit BIST is used to generate Ethernet packets. The BIST can be used to verify operations of all three speed modes. The speed mode can be established through auto-negotiation or manual forced mode ...
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Configuration (Continued) During transmit BIST operation the transmit path (TXD[7:0]) of the GMII / MII is disabled. All generated pack- ets will be sent out to the MDI path unless the loopback mode is enabled. In that case the ...
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... Functional Description The DP83865 is a full featured 10/100/1000 Ethernet Phys- ical layer (PHY) chip. It consists of a digital 10/100/1000 Mb/s core with a common TP interface. It also has a com- bined versitle MAC interface that is capable of interfacing with MII and GMII controller interfaces. In this section, the following topics are covered: — ...
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Functional Description Data Scrambler and Symbol LSFR Scr [32:0] n Sign Scrambler Word Generator g( ...
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Functional Description PARTIAL RESPONSE PULSE SHAPE CODING 5-LEVEL PAM-5 TO 17-LEVEL PAM SIGN PAM-5 SCRAMBLER 3-bits/sample 0.75 0.75 X(k) + 0.25 X(k-1) PMA Transmitter Block PAM-5 w ith PR (.7 5+.2 5T) 1.200 1.000 0.800 0.600 0.400 0.200 0.000 ...
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... SLAVE mode operations. 4.5 Gigabit MII (GMII) The Gigabit Media Independent Interface (GMII) is intended for use between Ethernet PHYs and Station Man- agement (STA) entities and is selected by either hardware or software configuration. The purpose of GMII is to make various physical media transparent to the MAC layer. ...
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Functional Description The mapping of the MAC interface is illustrated below in Table 51. Table 51. GMII/RGMII/MII Mapping GMII RGMII RXD[3:0] RX[3:0] RXD[4:7] RX_DV RCK RX_ER RXDV_ER RX_CLK RGMII_SEL1 TXD[3:0] TX[3:0] TXD[4:7] TX_EN TXEN_ER TX_ER GTX_CLK TCK COL CRS ...
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... PHY output skew is at +500 ps would be 2.3 ns. The 3COM mode clock delay is implemented internal in the DP83865DVH. The HP or 3COM mode can be selected at register 0x12.13:12. 4.6.3 10/100 Mbps Mode When RGMII interface is working in the 100 Mbps mode, the Ethernet Media Independent Interface (MII) is imple- mented by reducing the clock rate to 25 MHz ...
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Functional Description TX_CLK DIVIDER FROM PGM 100BASE-X LOOPBACK Figure 6. 10BASE-T/100BASE-TX Transmit Block Diagram 4.7.5 100BASE-T Code-group Encoding and Injection The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This ...
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Functional Description dB. The DP83865 uses the PHYADDR[4:0] value to set a unique seed value for the scramblers. The resulting energy generated by each channel is out of phase with respect to each channel, thus reducing the overall electro-magnetic ...
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Functional Description 4.7.9 MLT-3 Converter / DAC / Line Driver The Binary to MLT-3 conversion is accomplished by con- verting the serial NRZI data stream output from the NRZI encoder into two binary data streams with alternately NRZI_in MLT-3_plus ...
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Functional Description RXD[3:0] / 10BASE-T RX_ER 4-BIT NIBBLE DEMUX MANCHESTER TO NRZ DECODER CLOCK & DATA RECOVERY RECEIVER 10BASE-T Figure 8. 10BASE-T/100BASE-T Receive Block Diagram after the last bit, carrier sense is de-asserted. Receive clock stays active for at ...
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Functional Description in potentially serious BLW. The digital oscilloscope plot provided in Figure 9 illustrates the severity of the BLW event that can theoretically be generated during 100BASE-TX packet transmission. This event consists of approximately 800 ...
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Functional Description The CRM is implemented using an advanced digital Phase Locked Loop (PLL) architecture that replaces sensitive analog circuitry. Using digital PLL circuitry allows the DP83865 to be manufactured and specified to tighter toler- ances. 4.8.9 MLT-3 to ...
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Functional Description — Serial Management Preample Suppression — PHY Address Sensing — MII Data Interface — MII Isolate Mode — Status LED’s 4.9.1 Serial Management Register Access The serial management MII specification defines a set of thirty-two 16-bit status ...
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Functional Description MDC Z MDIO (STA Opcode PHY Address Idle Start (Write) (PHYAD = 0Ch) 4.9.4 PHY Address Sensing The DP83865 provides five PHY ...
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... Design Guide The design guide in conjunction with the Reference Design Schematics/BOM is intended to provide information to assist in the design and layout of the DP83865 Gigabit Ethernet Transceiver. The design guide covers the follow- ing topics: — Hardware Reset — Clocks — Power Supply Decoupling — ...
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Design Guide (Continued) between the ground and VDD plane also minimizes EMI radiation. Any through-hole clock oscillator component should be mounted as flat and as close to the PCB as possible. Excessive leads should be trimmed. Provide a ground ...
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Design Guide (Continued 1 Low pass filter for 1V8_AVDD2 only Typical supply bypassing (Near pins of the device 1 Low pass filter for 1V8_AVDD3 ...
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Design Guide (Continued) Do NOT cross plane split GND or power plane Figure 17. Signal crossing a plane split 5.6 Layout Notes on MAC Interface Trace Impedance All the signal traces of MII and GMII should be impedance controlled. ...
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... RJ-45 Connections The magnetics isolates local circuitry from other equipment that Ethernet connects to. The IEEE isolation test places stress on the isolated side to test the dielectic strength of the isolation. The center tap of the isolated winding has a "Bob Smith" termination through cap to chassis ground ...
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Design Guide (Continued) board space, the adjacent unused input pins can be grouped and tied together with a single resistor. The number of unused pins and which pins become unused pins highly depend on the individual application the DP83865 ...
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Design Guide (Continued) Table 56. Recommended Crystal Oscillators Manufacturer Vite Technology 25 MHz 7 Oscillator www.viteonline.com Raltron 25 MHz 7 Oscillator www.raltron.com Pericom www.saronix.com Abracon www.abracon.com Pletronics www.pletronics.com Note: Contact Oscillator manufactures for ...
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Design Guide (Continued) 5.13.2 Magnetics It is important to select the compoment that meets the requirements. Per IEEE 802.3ab Clause 40.8, the compo- nent requirements are listed in Table 57. transformer winding should have the configuration shown in Figure ...
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Electrical Specifications Absolute Maximum Ratings Supply Voltage IO_VDD Supply Voltage CORE_VDD, 1V8_AVDD1, 1V8_AVDD2 Supply Voltage 2V5_AVDD1, 2V5_AVDD2 Input Voltage (DC ) -0.5V to IO_VDD + 0.5V IN Output Voltage (DC ) -0.5V to IO_VDD + 0.5V OUT Storage Temperature ...
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Electrical Specifications Symbol Pin Types Parameter V I Input Low IL I/O Voltage non-R/GMII I/O_Z V O, Output High OH I/O Voltage non-R/GMII I/O_Z V O, Output Low OL I/O Voltage non-R/GMII I/O_Z R strap Strap PU/PD internal resistor ...
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Electrical Specifications 6.2 Reset Timing V 1.8V (core, analog), DD 2.5V (I/O, analog), 3.3V (I/O if applicable) CLK_IN RESET MDC Latch-In of Hardware Configuration Pins CLK_TO_MAC Parameter Description T1 Reference clock settle time The reference clock must be stable ...
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Electrical Specifications 6.3 Clock Timing CLK_IN Parameter Description T6 CLK_IN Duty Cycle T7 CLK_IN CLK_IN frequency (25 MHz +/-50 ppm) 6.4 1000 Mb/s Timing 6.4.1 GMII Transmit Interface Timing GTX_CLK T10 TXD[7:0], TX_EN, TX_ER ...
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Electrical Specifications 6.4.2 GMII Receive Timing RX_CLK T15 RXD[7:0] RX_DV RX_ER T18 MDI Begin of Frame Parameter T15 RX_CLK to RXD, RX_DV and RX_ER delay T16 RX_CLK Duty Cycle T17 RX_CLK T18 MDI to GMII ...
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Electrical Specifications 6.5 RGMII Timing 6.5.1 Transmit and Receive Multiplexing and Timing TX [3:0] TXEN_ER TCK RCK RX [3:0] RXDV_ER Parameter Clock skew (at receiver, PHY), HP mode skewT Clock skew (at receiver, ...
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Electrical Specifications 6.6 100 Mb/s Timing 6.6.1 100 Mb/s MII Transmit Timing TX_CLK TXD[3:0], TX_EN, TX_ER MDI Parameter T19 TXD[3:0], TX_EN and TX_ER Setup to T20 TXD[3:0], TX_EN and TX_ER Hold from T21 TX_CLK Duty Cycle T22 MII to ...
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Electrical Specifications 6.7 10 Mb/s Timing 6.7.1 10 Mb/s MII Transmit Timing TX_CLK TXD[3:0], TX_EN, TX_ER MDI Parameter T26 TXD[3:0], TX_EN and TX_ER Setup to T27 TXD[3:0], TX_EN and TX_ER Hold from T28 TX_CLK Duty Cycle T29 MII to ...
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Electrical Specifications 6.8 Loopback Timing GTX_CLK TX_CLK TX_EN TXD[7:0] TXD[3:0] CRS RX_CLK RX_DV RXD[7:0] RXD[3:0] Parameter Description T33 TX_EN to RX_DV Loopback Note: During loopback (all modes) both the TD outputs remain inactive by default. (Continued) Valid Data T33 ...
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Electrical Specifications 6.9 Serial Management Interface Timing MDC MDIO (output) MDC MDIO (input) Parameter Description T34 MDC Frequency T35 MDC to MDIO (Output) Delay Time T36 MDIO (Input) to MDC Setup Time T37 MDIO (Input) to MDC Hold Time ...
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Electrical Specifications 6.10 Power Consumption Symbol Pin Types Parameter I 1V8_AVDD, 1V8 1V8_1000 Core_VDD cur- rent I 2V5_AVDD cur- 2V5_1000 rent I IO_VDD current 2V5_IO_1000 I IO_VDD current 3V3_IO_1000 I 1V8_AVDD, 1V8 1V8_100 Core_VDD cur- rent I 2V5_AVDD, 2V5_100 ...
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Frequently Asked Questions 7 need to access any MDIO register to start up the PHY? A: The answer is no. The PHY is a self contained device. The initial settings of the PHY are configured by the ...
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... Broadcom BCM5400 from ever linking to an IEEE 802.3ab compliant part. This problem was observed in early inter-operability testing at National Semiconductor. A solution was put together that allows the DP83865 to inter-operate with any IEEE 802.3ab compliant Gigabit PHY as well as with earlier revi- sions of the BCM5400 that are non compliant ...
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... DP83865 Reference Design (Demo board, Schematics, BOM, Gerber files.) — Application Note 1263 “DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer Design Guide” — Application Note 1337 “Design Migration from DP83861 to DP83865” — Application Note 1301 “Dual Foot Print Layout Notes for DP83865 Gig PHYTER V and DP83847 DS PHYTER II” ...
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NOTES www.national.com 85 ...
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... BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no “Banned Substances” as defined in CSP-9-111S2. ...