DP83815DVNG National Semiconductor, DP83815DVNG Datasheet
DP83815DVNG
Specifications of DP83815DVNG
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DP83815DVNG Summary of contents
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... CPU. The DP83815 can support full duplex 10/100 Mb/s transmission and reception, with minimum interframe gap. The DP83815 device is an integration of an enhanced version of the National Semiconductor PCI MAC/BIU (Media Access Controller/Bus Interface Unit) and a 3.3V CMOS physical layer interface. Features — ...
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Connection Diagram . . . . . . . . . . . . . . . . . . 4 1.1 144 LQFP Package (VNG ...
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... Entering WOL Mode . . . . . . . . . . . . . . . . . . . . . . . 90 6.5.2 Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 3-1 DP83815 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3-2 MAC/BIU Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3-3 Ethernet Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 3-4 DSP Physical Layer Block Diagram Figure 3-5 LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 3-6 100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 3-7 Binary to MLT-3 conversion ...
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... GNTN 63 REQN 64 PCIVSS1 65 AD31 66 AD30 67 AD29 68 PCIVDD1 69 AD28 70 AD27 71 AD26 72 Pin1 Identification DP83815 Order Number DP83815DVNG See NS Package Number VNG144A 4 144 MA2/LED100N 143 MA1/LED10N MA0/LEDACTN 142 MD7 141 MD6 140 MD5 139 MD4/EEDO 138 VDDIO5 137 VSSIO5 136 MD3 135 MD2 ...
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Connection Diagram (Continued) 1.2 160 pin LBGA Package (UJB) Pin A1 Identification (Marked on Top Top View Order Number DP83815DUJB See NS Package Number UJB160A ...
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Pin Description PCI Bus Interface LQFP Pin Symbol No(s) AD[31-0] 66, 67, 68, 70, K3, K2, K4, 71, 72, 73, 74, L3, L2, M1, 78, 79, 81, 82, 83, 86, 87, 88, N5, M5, L5, 101, 102, 104, N6, ...
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Pin Description (Continued) PCI Bus Interface LQFP Pin Symbol No(s) PERRN 97 REQN 64 RSTN 62 SERRN 98 STOPN 96 TRDYN 93 PMEN/ 59 CLKRUNN 3VAUX 122 PWRGOOD 123 LBGA Pin No(s) Dir N9 I/O Parity Error: The DP83815 ...
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Pin Description (Continued) Media Independent Interface (MII) LQFP Pin Symbol No(s) COL 28 CRS 29 MDC 5 MDIO 4 RXCLK 6 RXD3/MA9, 12, 11, 10, 7 A9, B9, D10, RXD2/MA8, RXD1/MA7, RXD0/MA6 RXDV/MA11 15 RXER/MA10 14 RXOE 13 TXCLK ...
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Pin Description (Continued) 100BASE-TX/10BASE-T Interface LQFP Pin Symbol No(s) TPTDP, TPTDM 54, 53 TPRDP, 46, 45 TPRDM BIOS ROM/Flash Interface LQFP Pin Symbol No(s) MCSN 129 MD7, MD6, MD5, 141, 140, 139, MD4/EEDO, MD3, 138, 135, 134, MD2, 133, ...
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Pin Description (Continued) Clock Interface LQFP Pin Symbol No( LED Interface LQFP Pin Symbol No(s) LEDACTN/MA0 142 LED100N/MA2 144 LED10N/MA1 143 Serial EEPROM Interface LQFP Pin Symbol No(s) EESEL 128 EECLK/MA4 2 EEDI/MA3 1 EEDO/MD4 ...
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Pin Description (Continued) External Reference Interface LQFP Pin Symbol No(s) VREF 40 No Connects LQFP Pin Symbol No(s) NC 34, 42, 43, 48 A1, A13, A14, B3, B13, B14, D4, F3, F4, G2, M2, M3, N1, N2, N13, N14, ...
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Pin Description (Continued) Supply Pins LQFP Pin Symbol No(s) SUBGND1, 37, 49, 126 B2, E1, G12 SUBGND2, SUBGND3 RXAVDD1, 39, 47 RXAVDD2 RXAVSS1, 38, 44 RXAVSS2 TXIOVSS1, 52, 55 TXIOVSS2 TXDVDD 56 TXDVSS 51 MACVDD1, 58,125 MACVDD2 MACVSS1, 57, ...
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Functional Description DP83815 consists of a MAC/BIU Controller/Bus Interface Unit), a physical layer interface, SRAM, and miscellaneous support logic. The MAC/BIU includes the PCI bus, BIOS ROM and EEPROM interfaces, TPRDP/M 25 MHz Clk SRAM RX-2 KB SRAM RXFilter ...
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Functional Description PCI Bus 32 Interface 32 32 93C46 Serial EEPROM 3.1 MAC/BIU The MAC/BIU is a derivative design from the DP83810 (Euphrates). The original MAC/BIU design has been optimized to improve logic efficiency and enhanced ...
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Functional Description Little Endian (CFG:BEM=0): The byte orientation for receive and transmit data in system memory is as follows Byte 3 Byte 2 Byte 1 MSB C/BE[3] C/BE[2] C/BE[1] Big Endian (CFG:BEM=1): The byte ...
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... Functional Description The standard 802.3 Ethernet packet consists of the following fields: Preamble (PA), Start of Frame Delimiter (SFD), Destination Address (DA), Source Address (SA), Length (LEN), Data and Frame Check Sequence (FCS). All fields are fixed length except for the data field. During reception, the PA, SFD and FCS are stripped. During transmission, the DP83815 generates and appends the PA, SFD and FCS ...
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Functional Description POWER ON CONFIGURATION PINS TX_DATA TX_DATA TRANSMIT CHANNELS & STATE MACHINES 100 MB/S 10 MB/S 4B/5B ENCODER NRZ TO MANCHESTER SCRAMBLER ENCODER PARALLEL TO SERIAL LINK PULSE GENERATOR NRZ TO NRZI ENCODER TRANSMIT BINARY TO FILTER MLT-3 ...
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... For further detail regarding Auto-Negotiation, refer to Clause 28 of the IEEE 802.3u specification. The DP83815 supports four different Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex), so the inclusion of Auto-Negotiation ensures that the highest performance protocol will be selected based on the advertised ability of the Link Partner ...
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Functional Description register is set to a one. If configured for parallel detect mode, and any condition other than a single good link occurs, then the parallel detect fault bit will set to a one, bit 4 of the ...
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Functional Description 3.6 Half Duplex vs. Full Duplex The DP83815 supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds. Half-duplex is the standard, traditional mode of operation which relies on the CSMA/CD protocol ...
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Functional Description FROM CGM BP_4B5B 3.9.1 Code-group Encoding and Injection The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This conversion is required to allow control data to be combined ...
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Functional Description 3.9.3 NRZ to NRZI Encoder After the transmit data stream has been serialized and scrambled, the data must be NRZI encoded in order to comply with the TP-PMD standard for 100BASE-TX transmission over Category-5 un-shielded twisted pair ...
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Functional Description Name INVALID CODES The 100BASE-TX MLT-3 signal sourced by the TD± common driver output pins is slew rate controlled. This should be considered when selecting AC coupling ...
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Functional Description RXCLK LINK INTEGRITY MONITOR RX_DATA VALID SSD DETECT BP_SCR CLOCK CLOCK RECOVERY MODULE Subject to change without notice. (Continued) RXD(3:0)/RXER BP_RX MUX MUX BP_4B5B 4B/5B DECODER SERIAL TO PARALLEL CODE GROUP ALIGNMENT MUX DESCRAMBLER NRZI TO NRZ ...
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Functional Description 3.10.3 Digital Adaptive Equalization When transmitting data at high speeds over copper twisted pair cable, frequency dependent attenuation becomes a concern. In high-speed twisted pair signalling, the frequency content of the transmitted signal can vary greatly during ...
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Functional Description Figure 3-10 EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT V cable 2ns/div Figure 3-11 MLT-3 Signal Measured at AII after 0 meters of CAT V cable 3.10.4 Line Quality Monitor ...
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Functional Description 3.10.6 Clock Recovery Module The Clock Recovery Module (CRM) accepts 125 Mb/s MLT3 data from the equalizer. The DPLL locks onto the 125 Mb/s data stream and extracts a 125 MHz recovered clock. The extracted and synchronized ...
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Functional Description 3.11 10BASE-T Transceiver Module The 10BASE-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision, heartbeat, loopback, jabber, and link integrity functions, as defined in the standard. An external filter is not required on ...
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Functional Description 3.11.5 Jabber Function The jabber function monitors the DP83815's output and disables the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors the transmitter and disables the transmission if ...
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Functional Description 3.12.3 MII Serial Management Access Management access to the Management Data Clock (MDC) and Management Data Input/Output (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is bi-directional and ...
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Functional Description MDC Z MDIO (STA PHY Address Opcode Idle Start (Write) (PHYAD = 0Ch) The receive interface consists of a nibble wide data ...
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... This field is read-only and is set to the device ID assigned by National Semiconductor to the DP83815, which is 0020h. 15-0 VENID Vendor ID This field is read-only and is set to a value of 100Bh which is National Semiconductor's PCI Vendor ID. Table 4-1 Configuration Register Map Description Configuration Identification Register Configuration Command and Status Register ...
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Register Set (Continued) 4.1.2 Configuration Command and Status Register The CFGCS register has two parts. The upper 16-bits (31-16) are devoted to device status. A status bit is reset whenever the register is written, and the corresponding bit location ...
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... When set, DP83815 responds to I/O space accesses. When reset, DP83815 ignores I/O space accesses. 4.1.3 Configuration Revision ID Register This register stores the silicon revision number, revision number of software interface specification and lets the configuration software know that Ethernet controller in the class of network controllers. Tag: CFGRID Offset: 08h Bit ...
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Register Set (Continued) 4.1.4 Configuration Latency Timer Register This register gives status and controls such miscellaneous functions as BIST, Latency timer and Cache line size. Tag: CFGLAT Offset: 0Ch Bit Bit Name 31 BISTCAP BIST Capable Reads will always ...
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Register Set (Continued) 4.1.6 Configuration Memory Address Register This register specifies the Base Memory address which is required to build an address map during configuration. It also specifies the number of bytes required as well as an indication that ...
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Register Set (Continued) 4.1.8 Boot ROM Configuration Register Tag: CFGROM Offset: 30h Bit Bit Name 31-16 ROMBASE ROM Base Address Set to the base address for the boot ROM. 15-11 ROMSIZE ROM Size Set to 0 indicating a requirement ...
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Register Set (Continued) 4.1.10 Configuration Interrupt Select Register This register stores the interrupt line number as identified by the POST software that is connected to the interrupt controller as well as DP83815 desired settings for maximum latency and minimum ...
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Register Set (Continued) Bit Bit Name 24-22 AUX_CURRENT Aux_Current This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. If PMEN generation from D3cold is not supported by the function(PMCAP[31]), this field returns a value ...
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Register Set (Continued) 4.2 Operational Registers The DP83815 provides the following set of operational registers mapped into PCI memory space or I/O space. Writes to reserved register locations are ignored. Reads to reserved register locations return undefined values. Offset ...
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Register Set (Continued) 4.2.1 Command Register This register is used for issuing commands to DP83815. These commands are issued by setting the corresponding bits for the function. A global software reset along with individual reset and enable/disable for transmitter ...
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Register Set (Continued) 4.2.2 Configuration and Media Status Register This register allows configuration of a variety of device and phy options, and provides phy status information. Tag: CFG Offset: 0004h Bit Bit Name 31 LNKSTS Link Status Link status ...
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Register Set (Continued) Bit Bit Name 10 PHY_RST Reset internal Phy Asserts reset to internal phy. Can be used to cause phy to reload options from the CFG register. This bit does not self clear when set. R/W 9 ...
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... In the above table: N denotes the value is dependent on the ethernet MAC ID Number. X denotes the value is dependent on the checksum value. Size: 32 bits Access: Read Write Description Configuration/Operation Register Bits CFGSID[0:15] CFGSID[16:31] CFGINT[24:31],CFGINT[16:23] CFGCS[20],PMCAP[31],PMCAP[21],PMCSR[8], ...
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... PMATCH[47:0] can be accessed via the combination of the RFCR (offset 0048h) and RFDR (offset 004Ch) registers. PMATCH holds the Ethernet address info. See Section 3.3.3. The lower 8 bits of the checksum value should be 55h. For the upper 8 bits, add the top 8 data bits to the lower 8 data bits for each address. Sum the resultant 8 bit values for all addresses and then add 55h. Take the 2’ ...
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Register Set (Continued) 4.2.6 Interrupt Status Register This register indicates the source of an interrupt when the INTA pin goes active. Enabling the corresponding bits in the Interrupt Mask Register (IMR) allows bits in this register to produce an ...
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Register Set (Continued) Bit Bit Name 7 TXDESC Tx Descriptor This event is signaled after a transmit descriptor when the INTR bit in the CMDSTS field has been updated. 6 TXOK Tx Packet OK This event is signaled after ...
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Register Set (Continued) Bit Bit Name 20 RTABT Received Target Abort When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 19-17 unused 16 RXSOVR Rx Status FIFO Overrun When this bit is ...
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Register Set (Continued) 4.2.8 Interrupt Enable Register The Interrupt Enable Register controls the hardware INTR signal. Tag: IER Offset: 0018h Bit Bit Name 31-1 unused 0 IE Interrupt Enable When set to 1, the hardware INTR signal is enabled. ...
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... ATP Automatic Transmit Padding Setting this bit to 1 causes the MAC to automatically pad small (runt) transmit packets to the Ethernet minimum size of 64 bytes. This allows driver software to transfer only actual packet data. Setting this bit to 0 disables the automatic padding function, forcing software to control runt padding. ...
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Register Set (Continued) Bit Bit Name 22-20 MXDMA Max DMA Burst Size per Tx DMA Burst This field sets the maximum size of transmit DMA data bursts according to the following table: 000 = 128 32-bit words (512 bytes) ...
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Register Set (Continued) 4.2.12 Receive Configuration Register This register is used to set the receive configuration for DP83815. Receive properties such as accepting error packets, runt packets, setting the receive drain threshold etc. are controlled here. Tag: RXCFG Offset: ...
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Register Set (Continued) Bit Bit Name 5-1 DRTH Rx Drain Threshold Specifies the drain threshold in units of 8 bytes. When the number of bytes in the receive FIFO reaches this value (times 8), or the FIFO contains a ...
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Register Set (Continued) 4.2.13.1 CLKRUNN Function CLKRUNN is a dual-function optional signal used by the central PCI clock resource to indicate clock status (i.e. PCI clock running normally or slowed/stopped), and it is used by PCI devices ...
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Register Set (Continued) 4.2.14 Wake Command/Status Register The WCSR register is used to configure/control and monitor the DP83815 Wake On LAN logic. The Wake On LAN logic is used to monitor the incoming packet stream while in a low-power ...
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Register Set (Continued) Bit Bit Name 5 WKPAT0 Wake on Pattern 0 match Enable wake on match of pattern 0. R/W 4 WKARP Wake on ARP Enable wake on ARP packet detection. R/W 3 WKBCP Wake on Broadcast Enable ...
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Register Set (Continued) 4.2.15 Pause Control/Status Register The PCR register is used to control and monitor the DP83815 Pause Frame reception logic. The Pause Frame reception Logic is used to accept 802.3x Pause Frames, extract the pause length value, ...
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Register Set (Continued) 4.2.16 Receive Filter/Match Control Register The RFCR register is used to control and configure the DP83815 Receive Filter Control logic. The Receive Filter Control Logic is used to configure destination address filtering of incoming packets. Tag: ...
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Register Set (Continued) Bit Bit Name 9-0 RFADDR Receive Filter Extended Register Address Selects which internal receive filter register is accessible via RFDR: Perfect Match Register (PMATCH) 000h 002h 004h Pattern Count Registers (PCOUNT) 006h 008h SecureOn Password Register ...
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Register Set (Continued) 4.2.18 Receive Filter Logic The Receive Filter Logic supports a variety of techniques for qualifying incoming packets. options include Accept All Broadcast, Accept All Multicast and Accept All Unicast packets. These options are enabled by setting ...
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Register Set (Continued) Pattern3Word7F Pattern2Word7F Pattern3Word7E Pattern2Word7E Pattern3Word1 Pattern2Word1 Pattern3Word0 Pattern2Word0 Pattern1Word3F Pattern0Word3F Pattern1Word3E Pattern0Word3E Pattern1Word1 Pattern0Word1 Pattern1Word0 Pattern0Word0 Bit# Figure 4-1 Pattern Buffer Memory - 180h words (word = 18bits) byte1 byte0 byte1 byte0 byte1 byte0 byte1 byte0 ...
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Register Set (Continued) Example: Pattern match on the following destination addresses: 02-00-03-01-04-02 12-10-13-11-14-12 22-20-23-21-24-22 32-30-33-31-34-32 set $PATBUF01 = 280 set $PATBUF23 = 300 # write counts iow l $RFCR (0006) iow l $RFDR (0406) iow l $RFCR (0008) iow ...
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Register Set (Continued) Accept on Multicast or Unicast Hash Multicast and Unicast addresses may be further qualified by use of the receive filter hash functions. An internal 512 bit (64 byte) RAM-based hash table is used to perform imperfect ...
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... Offset: 0058h Bit Bit Name 31-16 unused (reads return 0) 15-0 Rev Revision Level SRR register value for the DP83815 silicon. DP83815CVNG DP83815DVNG/UJB 00000403h Size: 32 bits Access: Read Write Description Size: 32 bits Access: Read Write Description Size: 32 bits Access: Read Only Description 00000302h ...
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Register Set (Continued) 4.2.22 Management Information Base Control Register The MIBC register is used to control access to the statistics block and the warning bits and to control the collection of management information statistics. Tag: MIBC Offset: 005ch Bit ...
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Register Set (Continued) 4.2.23 Management Information Base Registers The counters provide a set of statistics compliant with the following management specifications: MIB II, Ether-like MIB, and IEEE MIB. The values provided are accessed through the various registers as shown ...
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Register Set (Continued) 4.3 Internal PHY Registers The Internal Phy Registers are only 16 bits wide. Bits [31:16] are not used. In the following register definitions under the ‘Default’ heading, the following definitions hold true: — RW=Read Write access ...
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Register Set (Continued) Bit Bit Name 7 Collision Test Collision Test: Default Collision test enabled 0 = Normal operation When set, this bit will cause the COL signal to be asserted in response to the assertion ...
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... Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. National Semiconductor's IEEE assigned OUI is 080017h. Tag: PHYIDR1 ...
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Register Set (Continued) Bit Bit Name 9 T4 100BASE-T4 Support: Default 100BASE-T4 is supported by the local device 0 = 100BASE-T4 not supported 8 TX_FD 100BASE-TX Full Duplex Support: Default: dependent on setting of the ANEG_SEL ...
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Register Set (Continued) Bit Bit Name 5 10 10BASE-T Support 10BASE-T is supported by the Link Partner 0 = 10BASE-T not supported by the Link Partner 4:0 Selector Protocol Selection Bits: Link Partners’s binary encoded protocol selector. ...
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Register Set (Continued) Bit Bit Name 12 ACK2 Acknowledge2: Default Will comply with message 0 = Cannot comply with message Acknowledge2 is used by the next page function to indicate that Local Device has the ability ...
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Register Set (Continued) Bit Bit Name 6 Remote Fault Remote Fault Remote Fault condition detected (cleared on read of BMSR (address 0x84h) register or by reset). Fault criteria: notification from Link Partner of Remote Fault via Auto-Negotiation ...
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Register Set (Continued) 4.3.10 MII Interrupt Control Register This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Link State Change, Jabber Event, Remote Fault, Auto-Negotiation Complete or any of the counters becoming half-full. ...
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Register Set (Continued) 4.3.12 False Carrier Sense Counter Register This counter provides information required to implement the “FalseCarriers” attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification. Tag: FCSCR Offset: 00D0h Bit Bit ...
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Register Set (Continued) Bit Bit Name 8 SD_OPTION Signal Detect Option Enhanced signal detect algorithm 0 = Reduced signal detect algorithm 7:6 Reserved Reserved: Read FORCE_100_OK Force 100 Mb/s Good Link: OR’ed with MAC_FORCE_LINK_100 ...
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Register Set (Continued) 4.3.16 10BASE-T Status/Control Register Tag: TBTSCR Offset: 00E8h Bit Bit Name 15:9 Unused 8 LOOPBACK_10_DIS 10BASE-T Loopback Disable: This bit is OR’ed with bit 14 (Loopback) in the BMCR Mb/s Loopback is enabled ...
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Register Set (Continued) 4.4 Recommended Registers Configuration For optimum performance of the DP83815, version noted as DP83815CVNG (SRR = 302h), the listed register modifications must be followed in sequence. The table below contains the register’s offset address value. The ...
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Buffer Management The buffer management scheme used on the DP83815 allows quick, simple and efficient use of the frame buffer memory. Frames are saved in similar formats for both transmit and receive. The buffer management scheme also uses separate ...
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Buffer Management (Continued Packet OK 26-16 --- 15-12 11-0 SIZE Descriptor Byte Count Set to the size in bytes of the data. Bit Tag Description 26 TXA Transmit Abort 25 TFU Transmit FIFO Underrun 24 CRS Carrier ...
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Buffer Management (Continued) Bit Tag Description 26 RXA Receive Aborted 25 RXO Receive Overrun 24-23 DEST Destination Class 22 LONG Too Long Packet Received 21 RUNT Runt Packet Received The size of the receive packet was less than 64 ...
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... Multiple Descriptor Packets A single packet may also cross descriptor boundaries. This is indicated by setting the MORE bit in all descriptors except the last one in the packet. Ethernet applications (bridges, switches, routers, etc.) can optimize memory utilization by using a single small buffer per receive ...
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... Buffer Management 5.2 Transmit Architecture The following figure illustrates the transmit architecture of the DP83815 10/100 Ethernet Controller. Software/Memory Transmit Descriptor link cmdsts ptr Packet When the CR:TXE bit is set to 1 (regardless of the current state), and the DP83815 transmitter is idle, then DP83815 will read the contents of the current transmit descriptor into the TxDescCache. The DP83815’ ...
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Buffer Management (Continued) State Event txIdle CR:TXE && !CTDD CR:TXE && CTDD txDescRefr XferDone txDescRead XferDone && OWN XferDone && !OWN txFIFOblock FifoAvail (descCnt == 0) && MORE (descCnt == 0) && !MORE txFragRead XferDone txDescWrite XferDone txAdvance link ...
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Buffer Management 5.2.2 Transmit Data Flow In the DP83815 transmit architecture, packet transmission involves the following steps: 1. The device driver receives packets from an upper layer available DP83815 allocated. The fragment information is copied from the ...
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Buffer Management 5.3 Receive Architecture The receive architecture is as "symmetrical" to the transmit architecture as possible. The receive buffer manager prefetches receive descriptors to prepare for incoming Receive Descriptor List link link cmdsts cmdsts ptr ptr When the ...
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Buffer Management (Continued) State Event rxIdle CR:RXE && !CRDD CR:RXE && CRDD rxDescRefr XferDone rxDescRead XferDone && !OWN XferDone && OWN rxFIFOblock FifoReady (descCnt == 0) && (rxPktBytes > 0) rxPktBytes == 0 rxFragWrite XferDone rxDescWrite XferDone rxAdvance link!= ...
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Buffer Management CR:RXE && CRDD rxDescRefr XferDone link = NULL rxAdvance XferDone rxDescWrite 5.3.2 Receive Data Flow With a bus mastering architecture, some number of buffers and descriptors for received packets must be pre-allocated when the DP83815 is initialized. ...
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... The packet must also meet the basic require- ments for the LAN technology chosen (e.g. ethernet frame). The specific data sequence consists of 16 du- plications of the MAC address of the machine to be awakened. The synchronization stream is defined as 6 bytes of FFh.” ...
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Power Management and Wake-On-LAN 6.4.1 D0 State The D0 state is the normal operational state of the device. The PME Enable bit should be set prevent packet filtering based on the settings in the Wake Control/Status ...
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Power Management and Wake-On-LAN 6.5.2 Wake Events If the device detects a wake event while in WOL mode, it will assert the PMEN pin low to signal the system that a wake event has occurred. The system should then ...
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DC and AC Specifications Absolute Maximum Ratings Supply Voltage ( 3.3 V PCI signaling, 5.0 V tolerant DC Input Voltage ( Output Voltage (V ) OUT Storage Temperature Range (T ) STG Power Dissipation ...
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DC and AC Specifications 7.2 AC Specifications 7.2.1 PCI Clock Timing PCICLK Number PCICLK Low Time 7.2.1.1 PCICLK High Time 7.2.1.2 PCICLK Cycle Time 7.2.1.3 7.2.2 X1 Clock Timing X1 Number X1 Low Time 7.2.2.1 X1 High Time 7.2.2.2 ...
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DC and AC Specifications 7.2.3 Power On Reset (PCI Active) Power Stable RSTN PCICLK Number RSTN Active Duration from PCICLK 7.2.3.1 stable Reset Disable to 1st PCI Cycle 7.2.3.2 EE Enabled EE Disabled Note 1: Minimum reset complete time ...
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DC and AC Specifications 7.2.5 POR PCI Inactive VDD T1 EESEL TPRD Number VDD stable to EE access 7.2.5.1 VDD indicates the digital supply (AUX power plane, except PCI bus power.) Guaranteed by design. EE Configuration load duration 7.2.5.2 ...
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DC and AC Specifications 7.2.6 PCI Bus Cycles The following table parameters apply to ALL the PCI Bus Cycle Timing Diagrams contained in this section. Number Input Setup Time 7.2.6.1 Input Hold Time 7.2.6.2 Output Valid Delay 7.2.6.3 Output ...
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DC and AC Specifications PCI Configuration Write PCICLK T1 T2 FRAMEN AD[31:0] Addr C/BEN[3:0] Cmd T2 T1 IDSEL T1 IRDYN TRDYN DEVSELN T1 T2 PAR PERRN PCI Bus Master Read PCICLK T3 T3 ...
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DC and AC Specifications PCI Bus Master Write PCICLK T3 FRAMEN T3 AD[31:0] Addr T3 C/BEN[3:0] Cmd IRDYN TRDYN DEVSELN PAR PERRN PCI Target Read PCICLK T2 T1 FRAMEN T1 T2 AD[31:0] Addr C/BEN[3:0] Cmd BE ...
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DC and AC Specifications PCI Target Write PCICLK T1 T2 FRAMEN AD[31:0] Addr C/BEN[3:0] Cmd T1 IRDYN TRDYN DEVSELN T1 T2 PAR PERRN PCI Bus Master Burst Read PCICLK T3 FRAMEN T4 T3 ...
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DC and AC Specifications PCI Bus Master Burst Write PCICLK T3 FRAMEN T3 AD[31:0] Addr T3 C/BEN[3:0] Cmd IRDYN TRDYN DEVSELN PAR PERRN PCI Bus Arbitration PCICLK T5 REQN GNTN (Continued Data Data Data T4 ...
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DC and AC Specifications 7.2.7 EEPROM Auto-Load EECLK EESEL EEDO EEDI Number EECLK Cycle Time 7.2.7.1 EECLK Delay from EESEL Valid 7.2.7.2 EECLK Low to EESEL Invalid 7.2.7.3 EECLK to EEDO Valid 7.2.7.4 EEDI Setup Time to EECLK 7.2.7.5 ...
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DC and AC Specifications 7.2.8 Boot PROM/FLASH T13 MCSN T17 MRDN MA[15:0] MD[7:0] MWRN Number Data Setup Time to MRDN Invalid 7.2.8.1 Address Setup Time to MRDN 7.2.8.2 Address Hold Time from MRDN Invalid 7.2.8.3 Address Invalid from MWRN ...
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DC and AC Specifications 7.2.9 100BASE-TX Transmit TPTD+/− T2 TPTD+/− eye pattern Parameter Description 100 Mb/s TPTD+/− Rise and 7.2.9.1 Fall Times 100 Mb/s Rise/Fall Mismatch 100 Mb/s TPTD+/− 7.2.9.2 Transmit Jitter Note: Normal Mismatch is the difference between ...
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DC and AC Specifications 7.2.10 10BASE-T Transmit End of Packet TPTD+/- TPTD+/- Parameter Description End of Packet High Time 7.2.10.1 (with ‘0’ ending bit) End of Packet High Time 7.2.10.2 (with ‘1’ ending bit) 7.2.11 10 Mb/s Jabber Timing ...
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DC and AC Specifications 7.2.12 10BASE-T Normal Link Pulse Parameter Description Pulse Width 7.2.12.1 Pulse Period 7.2.12.2 Note: These specifications represent both transmit and receive timings 7.2.13 Auto-Negotiation Fast Link Pulse (FLP) T1 Fast Link Pulse(s) Parameter Description Clock, ...
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DC and AC Specifications 7.2.14 Media Independent Interface (MII) MDC MDIO(output) MDIO(input) RXCLK RXD[3:0] RXDV,RXER TXCLK TXD[3:0] TXEN Number MDC to MDIO Valid 7.2.14.1 MDIO to MDC Setup 7.2.14.2 MDIO from MDC Hold 7.2.14.3 RXD to RXCLK Setup 7.2.14.4 ...
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... PHYSICAL DIMENSIONS inches (millimeters) unless otherwise noted Order Number: DP83815DVNG NS Package Number: VNG144A 107 www.national.com ...
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... BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no “Banned Substances” as defined in CSP-9-111S2. ...