SC16C752BIB48 NXP Semiconductors, SC16C752BIB48 Datasheet
SC16C752BIB48
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SC16C752B 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Rev. 6 — 30 November 2010 1. General description The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow ...
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... Internal test and loopback capabilities Fully prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, and CD) 3. Ordering information Table 1. Ordering information Type number Package Name SC16C752BIB48 LQFP48 SC16C752BIBS HVQFN32 1. For data bus D0, see Table 24 “Limiting SC16C752B Product data sheet ...
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... NXP Semiconductors 4. Block diagram SC16C752B DATA BUS IOR IOW CONTROL RESET REGISTER CSA CSB INTA, INTB INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB Fig 1. Block diagram SC16C752B Product data sheet 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs AND ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Fig 3. SC16C752B Product data sheet 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs RXB 4 RXA 5 6 TXRDYB SC16C752BIB48 TXA 7 TXB 8 OPB 9 CSA 10 11 CSB 12 n.c. Pin configuration for LQFP48 terminal 1 index area ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin LQFP48 HVQFN32 CDA 40 - CDB 16 - CSA 10 8 CSB 11 9 CTSA 38 25 CTSB DSRA 39 - DSRB 20 - DTRA 34 - DTRB 35 - GND 17 13 INTA 30 21 INTB 29 20 IOR 19 14 SC16C752B Product data sheet 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin LQFP48 HVQFN32 IOW 15 12 n.c. 12, 24, - 25, 37 OPA 32 22 OPB 9 7 RESET 36 24 RIA 41 - RIB 21 - RTSA 33 23 RTSB 22 15 RXA 5 4 RXB 4 3 RXRDYA 31 - RXRDYB 18 - TXA 7 5 TXB 8 6 TXRDYA 43 - TXRDYB XTAL1 13 10 ...
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... NXP Semiconductors 6. Functional description The SC16C752B UART is pin-compatible with the SC16C2550 UART. It provides more enhanced features. All additional features are provided through a special Enhanced Feature Register (EFR). The UART will perform serial-to-parallel conversion on data characters received from peripheral devices or modems, and parallel-to-parallel conversion on data characters transmitted by the processor ...
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... NXP Semiconductors UART 1 RX FIFO FIFO Fig 4. Auto flow control (auto-RTS and auto-CTS) example 6.2.1 Auto-RTS Auto-RTS data flow control originates in the receiver block (see on page in auto-RTS are stored in the TCR. RTSn is active if the RX FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTSn is de-asserted ...
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... NXP Semiconductors 6.2.2 Auto-CTS The transmitter circuitry checks CTSn before sending the next data byte. When CTSn is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTSn must be de-asserted before the middle of the last stop bit that is currently being sent ...
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... NXP Semiconductors There are two other enhanced features relating to software flow control: • Xon Any function (MCR[5]): Operation will resume after receiving any character after recognizing the Xoff character possible that an Xon1 character is recognized as an Xon Any character, which could cause an Xon2 character to be written to the receive FIFO. • ...
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... NXP Semiconductors 6.3.3 Software flow control example Fig 7. 6.3.3.1 Assumptions UART1 is transmitting a large text file to UART2. Both UARTs are using software flow control with single character Xoff (0Fh) and Xon (0Dh) tokens. Both have Xoff threshold (TCR[3:0] = Fh) set to 60, and Xon threshold (TCR[7:4] = 8h) set to 32. Both have the interrupt receive threshold (TLR[7:4] = Dh) set to 52 ...
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... NXP Semiconductors 6.4 Reset Table 4 Table 4. Register Interrupt Enable Register Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register Enhanced Feature Register Receiver Holding Register Transmitter Holding Register Transmission Control Register Trigger Level Register ...
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... NXP Semiconductors 6.5 Interrupts The SC16C752B has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of interrupts and the INTA/INTB signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bit 0 to bit 3 and bit 5 to bit 7. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5:0] ...
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... NXP Semiconductors 6.5.1 Interrupt mode operation In interrupt mode (if any bit of IER[3: the processor is informed of the status of the receiver and transmitter by an interrupt signal, INTA/INTB. Therefore not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced. Fig 8. ...
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... NXP Semiconductors 6.6 DMA operation There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by FCR[3]. In DMA mode 0 or FIFO disable (FCR[ DMA occurs in single character transfers. In DMA mode 1, multi-character (or block) DMA transfers are managed to relieve the processor for longer periods of time. ...
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... NXP Semiconductors 6.6.2 Block DMA transfers (DMA mode 1) Figure 11 trigger Fig 11. TXRDYn and RXRDYn in DMA mode 1 6.6.2.1 Transmitter TXRDYn is active when there is a trigger level number of spaces available. It becomes inactive when the FIFO is full. 6.6.2.2 Receiver RXRDYn becomes active when the trigger level has been reached, or when a time-out interrupt occurs ...
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... NXP Semiconductors 6.8 Break and time-out conditions An RX idle condition is detected when the receiver line, RXn, has been HIGH for 4 character time. The receiver line is sampled midway through each bit. When a break condition occurs, the TXn line is pulled LOW. A break condition is activated by setting LCR[6] ...
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... NXP Semiconductors Table 7. Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 Table 8. Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 ...
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... NXP Semiconductors Fig 13. Crystal oscillator connections 7. Register descriptions Each register is selected using address lines A0, A1, A2, and in some cases, bits from other registers. The programming combinations for register selection are shown in Table 9. Table [1] MCR[7] can only be modified when EFR[4] is set. [2] Accessed by a combination of address pins and register bits. ...
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... NXP Semiconductors Table 10 Table 10. SC16C752B internal registers Register Bit 7 [1] General register set RHR bit THR bit IER 0/CTS interrupt [2] enable FCR RX trigger level (MSB IIR FCR[ LCR DLAB MCR 1× or 1× [2] clock LSR 0/error in RX FIFO MSR SPR bit 7 ...
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... NXP Semiconductors Remark: Refer to the notes under 7.1 Receiver Holding Register (RHR) The receiver section consists of the Receiver Holding Register (RHR) and the Receiver Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX terminal. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the Line Control Register ...
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... NXP Semiconductors 7.3 FIFO Control Register (FCR) This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and receiver trigger levels, and selecting the type of DMA signalling. shows FIFO control register bit settings. Table 11. Bit Symbol ...
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... NXP Semiconductors 7.4 Line Control Register (LCR) This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. shows the Line Control Register bit settings. Table 12. Bit 1:0 ...
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... NXP Semiconductors 7.5 Line Status Register (LSR) Table 13 Table 13. Bit When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the receive FIFO (next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the receive FIFO is output directly onto the output data bus, DI[4:2], when the LSR is read ...
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... NXP Semiconductors 7.6 Modem Control Register (MCR) The MCR controls the interface with the mode, data set, or peripheral device that is emulating the modem. Table 14. Bit [1] MCR[7:5] can only be modified when EFR[4] is set, i.e., EFR[ write enable. SC16C752B Product data sheet 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Table 14 shows modem control register bit settings ...
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... NXP Semiconductors 7.7 Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the mode, data set, or peripheral device to the processor. It also indicates when a control input from the modem changes state. per channel. Table 15. ...
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... NXP Semiconductors 7.8 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, Xoff received, or CTSn/RTSn change of state from LOW to HIGH. The INTA/INTB output signal is activated in response to interrupt generation. Table 16. ...
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... NXP Semiconductors 7.9 Interrupt Identification Register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 17. Bit Symbol 7:6 IIR[7:6] 5 IIR[5] 4 IIR[4] 3:1 IIR[3:1] 0 IIR[0] The interrupt priority list is shown in Table 18. Priority level 7.10 Enhanced Feature Register (EFR) This 8-bit register enables or disables the enhanced features of the UART ...
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... NXP Semiconductors Table 19. Bit Symbol 5 EFR[5] 4 EFR[4] 3:0 EFR[3:0] Combinations of software flow control can be selected by programming these bits. 7.11 Divisor latches (DLL, DLM) These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLM stores the most significant part of the divisor. DLL stores the least significant part of the divisor ...
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... NXP Semiconductors 7.13 Trigger Level Register (TLR) This 8-bit register is pulsed to store the transmit and received FIFO trigger levels used for DMA and interrupt generation. Trigger levels from can be programmed with a granularity of 4. Table 21. Bit Symbol 7:4 TLR[7:4] 3:0 TLR[3:0] Remark: TLR can only be written to when EFR[4] = logic 1 and MCR[6] = logic 1. If TLR[3:0] or TLR[7:4] are logic 0, the selectable trigger levels via the FIFO Control Register (FCR) are used for the transmit and receive FIFO trigger levels ...
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... NXP Semiconductors 8. Programmer’s guide The base set of registers that is used during high-speed data transfer have a straightforward access method. The extended function registers require special access bits to be decoded along with the address lines. The following guide will help with programming these registers. Note that the descriptions below are for individual register access ...
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... NXP Semiconductors Table 23. Command Set TX FIFO and RX FIFO thresholds to VALUE Read FIFO Rdy register Set prescaler value to divide-by-1 Set prescaler value to divide-by-4 × sign here means bit-AND. [1] SC16C752B Product data sheet 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Register programming guide … ...
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... NXP Semiconductors 9. Limiting values Table 24. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V voltage on any other pin n T ambient temperature amb T storage temperature stg 10. Static characteristics Table 25. Static characteristics ± 2 Symbol Parameter ...
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... NXP Semiconductors [5] Except XTAL2 typical. OL These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150 °C. The customer is [6] responsible for verifying junction temperature. [7] Measurement condition, normal operation other than Sleep mode °C. Full duplex serial activity on all two serial (UART) channels at the clock frequency specified in the V = 3.3 V ...
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... NXP Semiconductors Table 26. Dynamic characteristics − ° ° + 2.5 V, 3.3 V amb CC Symbol Parameter t data set-up time su2 t set-up time from IOW or IOR assertion to su3 XTAL1 clock LOW-to-HIGH transition t IOR strobe width w1 t IOW strobe width w2 [1] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches. ...
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... NXP Semiconductors su1 CSA, CSB IOW Fig 15. General write timing IOW RTSA, RTSB change of state DTRA, DTRB CDA, CDB CTSA, CTSB DSRA, DSRB INTA, INTB IOR RIA, RIB Fig 16. Modem input/output timing SC16C752B Product data sheet 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs ...
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... NXP Semiconductors RXA, RXB INTA, INTB IOR Fig 17. Receive timing RXA, RXB RXRDYA RXRDYB IOR Fig 18. Receive ready timing in non-FIFO mode SC16C752B Product data sheet 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Start bit data bits ( data bits ...
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... NXP Semiconductors RXA, RXB RXRDYA RXRDYB IOR Fig 19. Receive ready timing in FIFO mode TXA, TXB INTA, INTB active IOW Fig 20. Transmit timing SC16C752B Product data sheet 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs start bit data bits ( ...
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... NXP Semiconductors TXA, TXB IOW active byte #1 TXRDYA TXRDYB Fig 21. Transmit ready timing in non-FIFO mode TXA, TXB IOW active byte #64 t d17 TXRDYA TXRDYB Fig 22. Transmit ready timing in FIFO mode SC16C752B Product data sheet 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs ...
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... NXP Semiconductors 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 29. Acronym CPU DMA FIFO TTL UART 15. Revision history Table 30. Revision history Document ID Release date SC16C752B v ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 7 6.1 Trigger levels . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 Hardware flow control . . . . . . . . . . . . . . . . . . . . 7 6.2.1 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2.2 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.3 Software flow control . . . . . . . . . . . . . . . . . . . . 9 6 ...