DSPIC30F2010-30I/SPG Microchip Technology, DSPIC30F2010-30I/SPG Datasheet
DSPIC30F2010-30I/SPG
Specifications of DSPIC30F2010-30I/SPG
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DSPIC30F2010-30I/SPG Summary of contents
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... Farnell Codes 7314841- 4892 7314906 - 4973 Power Conversion Family 2004 Microchip Technology Inc. dsPIC30F Data Sheet Motor Control and High Performance Digital Signal Controllers Advance Information DS70082E ...
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... PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U ...
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... external interrupt sources • Timer module with programmable prescaler five 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • 16-bit Capture input functions 2004 Microchip Technology Inc. Peripheral Features (Continued): • 16-bit Compare/PWM output functions - Dual Compare mode available TM • ...
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... Conversion available during Sleep and Idle • Programmable Low Voltage Detection (PLVD) • Programmable Brown-out Detection and Reset generation dsPIC30F Motor Control and Power Conversion Family Program SRAM Device Pins Mem. Bytes/ Bytes Instructions dsPIC30F2010 28 12K/4K 512 dsPIC30F3010 28 24K/8K 1024 dsPIC30F4012 28 48K/16K 2048 ...
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... Pin Diagrams 28-Pin QFN AN2/SS1/CN4/RB2 AN3/INDX/CN5 RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 OSC1/CLKIN OSC2/CLKO/RC15 Note: Pinout subject to change. 2004 Microchip Technology Inc PWM2L/RE2 2 20 PWM2H/RE3 3 19 PWM3L/RE4 dsPIC30F2010 4 18 PWM3H/RE5 PGC/EMUC/U1RX/SDI1/SDA/RF2 Advance Information dsPIC30F DS70082E-page 3 ...
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... PWM2L/RE2 24 6 PWM2H/RE3 23 7 PWM3L/RE4 PWM3H/RE5 9 DD OSC1/CLKI PGC/EMUC/U1RX/SDI1/SDA/RF2 12 PGD/EMUD/U1TX/SDO1/SCL/RF3 FLTA/INT0/SCK1/OCFA/RE8 14 15 EMUC2/OC1/IC1/INT1/RD0 1 MCLR REF SS +/CN2/RB0 REF -/CN3/RB1 PWM1L/RE0 26 4 PWM1H/RE1 PWM2L/RE2 6 PWM2H/RE3 23 7 PWM3L/RE4 PWM3H/RE5 OSC1/CLKI PGC/EMUC/U1RX/SDI1/SDA/C1RX/RF2 12 17 PGD/EMUD/U1TX/SDO1/SCL/C1TX/RF3 FLTA/INT0/SCK1/OCFA/RE8 14 15 EMUC2/OC1/IC1/INT1/RD0 Advance Information 2004 Microchip Technology Inc. ...
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... EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD2/OC2/IC2/INT2/RD1 Note: Pinout subject to change. 40-Pin PDIP EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD2/OC2/IC2/INT2/RD1 Note: Pinout subject to change. 2004 Microchip Technology Inc. MCLR REF 2 39 +/CN2/RB0 AV REF 3 38 -/CN3/RB1 PWM1L/RE0 4 37 PWM1H/RE1 5 ...
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... Pin Diagrams (Continued) 44-Pin TQFP AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 AN6/OCFA/RB6 AN7/RB7 AN8/RB8 OSC1/CLKI OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 Note: Pinout subject to change. DS70082E-page dsPIC30F3011 Advance Information PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 RF0 RF1 U2RXRF4 U2TX/RF5 PGC/EMUC/U1RX/SDI1/SDA/RF2 2004 Microchip Technology Inc. ...
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... Pin Diagrams (Continued) 44-Pin TQFP AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 AN6/OCFA/RB6 AN7/RB7 AN8/RB8 OSC1/CLKI OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 Note: Pinout subject to change. 2004 Microchip Technology Inc dsPIC30F4011 Advance Information dsPIC30F PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 C1RX/RF0 C1TX/RF1 U2RXRF4 U2TX/RF5 PGC/EMUC/U1RX/SDI1/SDA/RF2 DS70082E-page 7 ...
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... MCLR 7 SS2/CN11/RG9 AN5/QEB/IC8/CN7/RB5 11 AN4/QEA/IC7/CN6/RB4 12 AN3/INDX/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 REF AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 Note: Pinout subject to change. DS70082E-page dsPIC30F5015 Advance Information EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 INT4/RD11 INT3/RD10 IC2/FLTB/INT2/RD9 IC1/FLTA/INT1/RD8 SS V OSC2/CLKO/RC15 OSC1/CLKIN V DD SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 U1RX/SDI1/RF2 EMUD3/U1TX/SDO1/RF3 2004 Microchip Technology Inc. ...
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... T2CK/RC1 5 T4CK/RC3 6 SCK2/CN8/RG6 7 SDI2/CN9/RG7 8 SDO2/CN10/RG8 9 MCLR 10 SS2/CN11/RG9 FLTA/INT1/RE8 14 FLTB/INT2/RE9 15 AN5/QEB/CN7/RB5 16 AN4/QEA/CN6/RB4 AN3/INDX/CN5/RB3 17 18 AN2/SS1/LVDIN/CN4/RB2 19 PGC/EMUC/AN1/CN3/RB1 20 PGD/EMUD/AN0/CN2/RB0 Note: Pinout subject to change. 2004 Microchip Technology Inc dsPIC30F6010 Advance Information dsPIC30F EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS70082E-page 10 Advance Information 2004 Microchip Technology Inc. ...
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... Digital Signal Processor (DSP) functionality within a high performance 16-bit microcontroller architecture. 2004 Microchip Technology Inc. Figure 1-1 shows a sample device block diagram. Note: The device(s) depicted in this block dia- gram are representative of the correspond- ing device family. Other devices of the same family may vary in terms of number of pins and multiplexing of pin functions ...
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... OC3/RD2 OC4/RD3 OC5/CN13/RD4 OC6/CN14/RD5 OC7/CN15/RD6 OC8/CN16/UPDN/RD7 IC1/RD8 IC2/RD9 IC3/RD10 IC4/RD11 IC5/RD12 IC6/CN19/RD13 IC7/CN20/RD14 IC8/CN21/RD15 PORTD PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 FLTA/INT1/RE8 FLTB/INT2/RE9 PORTE C1RX/RF0 C1TX/RF1 U1RX/RF2 U1TX/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8 PORTF 2004 Microchip Technology Inc. ...
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... CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input 2004 Microchip Technology Inc. Description Analog input channels. AN0 and AN1 are also used for device programming data and clock inputs, respectively. Positive supply for analog module. Ground reference for analog module. ...
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... Synchronous serial clock input/output for I Synchronous serial data input/output for I 32 kHz low power oscillator crystal output. 32 kHz low power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Analog = Advance Information Analog input Output Power 2004 Microchip Technology Inc. ...
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... CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input 2004 Microchip Technology Inc. Description Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. UART1 Receive. UART1 Transmit. ...
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... NOTES: DS70082E-page 16 Advance Information 2004 Microchip Technology Inc. ...
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... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. The X AGU also supports bit-reversed addressing on destination effective addresses, to greatly simplify input or output data reordering for radix-2 FFT algorithms ...
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... All other instructions can set as well as clear the Z bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address instruction words. Advance Information 2004 Microchip Technology Inc. ...
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... AD39 DSP AccA Accumulators AccB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH 2004 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 0 ...
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... Fetch 1 1. MOV #0x55,W0 2. BTSC W1,#3 3. ADD W0,W1,W2 4. BRA SUB_1 5. SUB W0,W1,W3 6. Instruction @ address SUB_1 DS70082E-page Execute 1 Fetch 2 Execute 2 Fetch 3 Execute Execute 1 Fetch 2 Execute 2 Skip Taken Fetch 3 Flush Fetch 4 Advance Information Execute 4 Fetch 5 Flush Fetch SUB_1 2004 Microchip Technology Inc. ...
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... Figure 2-6. FIGURE 2-6: INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE GOTO, CALL Fetch 1 1. MOV #0x1234,W0 2. GOTO LABEL 2a.Second Word 3. Instruction @ address LABEL 4. BSET W1, #BIT3 2004 Microchip Technology Inc Execute 1 Fetch 2 Execute 2 R/W Cycle 1 ...
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... Fetch 1 1. MOV.b W0,[W1] 2. MOV.b [W1],PORTB 2a.Stall (NOP) 3. MOV.b W0,PORTB 8. Interrupt recognition execution. Section 5.0 for details on interrupts. DS70082E-page Execute 1 Fetch 2L NOP Fetch 2H Execute 2 Fetch Execute 1 Fetch 2 NOP Stall Execute 2 Fetch 3 Refer to Advance Information Execute Execute 3 2004 Microchip Technology Inc. ...
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... DIV.sd DIV.sw (or DIV.s) DIV.ud DIV.uw (or DIV.u) 2004 Microchip Technology Inc. The non-restoring divide algorithm requires one cycle for an initial dividend shift (for integer divides only), one cycle per divisor bit, and a remainder/quotient correc- tion cycle. The correction cycle is the last cycle of the ...
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... Automatic saturation on/off for AccB (SATB). 6. Automatic saturation on/off for writes to data memory (SATDW). 7. Accumulator (ACCSAT). Note: For CORCON layout, see Table 4-3. A block diagram of the DSP engine is shown in Figure 2-9. Advance Information operations, which Saturation mode selection 2004 Microchip Technology Inc. ...
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... FIGURE 2-9: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In 2004 Microchip Technology Inc. 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Advance Information dsPIC30F Round u Logic Zero Backfill DS70082E-page 25 ...
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... IF bit, the result must be explicitly shifted left by the user program after multiplication in order to obtain the correct result. Advance Information 1-N ). For fractional mode, a 16x16 mul- - -15 2 -30 , but has no other effect on the 2004 Microchip Technology Inc. ...
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... SB: AccB saturated (bit 31 overflow and saturation) or AccB overflowed into guard bits and saturated (bit 39 overflow and saturation) 2004 Microchip Technology Inc. 5. OAB: Logical and OB 6. SAB: Logical and SB The OA and OB bits are modified each time data passes through the adder/Subtractor ...
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... DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is pre- sented to the barrel shifter between bit positions for right shifts, and bit positions for left shifts. Advance Information 2004 Microchip Technology Inc. ...
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... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. User program space access is restricted to the lower 4M instruction word address range (0x000000 to 0x7FFFFE), for all accesses other than TBLRD/TBLWT, which use TBLPAG< ...
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... P<23:16> maps to the destination byte when byte select = 0; The destination byte will always when byte select = 1. 4. TBLWTH: Table Write High (refer to Section 6.0 for details on Flash Programming TBLRDL.B (Wn<0> TBLRDL.W TBLRDL.B (Wn<0> Advance Information 0 2004 Microchip Technology Inc. ...
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... The upper 8 bits should be programmed to force an illegal instruction to maintain machine robust- ness. Refer to the Programmer’s Reference Manual (DS70030) for details on instruction encoding. 2004 Microchip Technology Inc. TBLRDH TBLRDH.B (Wn<0> TBLRDH.B (Wn< ...
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... Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines the page in program space to which the upper half of data space is being mapped). DS70082E-page 32 0x0000 (1) PSVPAG 0x21 8 0x8000 23 Address Concatenation 15 23 0xFFFF Advance Information Program Space 0x108000 15 0 0x108200 0x10FFFF Data Read 2004 Microchip Technology Inc. ...
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... Device Configuration Registers Reserved DEVID (2) Note: These address boundaries may vary from one device to another. 2004 Microchip Technology Inc. 3.2 Data Address Space The core has two data spaces. The data spaces can be 000000 considered either separate (for some DSP instruc- ...
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... W8 and W9. Both address spaces are concurrently accessed only with the MAC class instructions. An example data space memory map is shown in Figure 3-8. Advance Information DATA ALIGNMENT LS Byte 0000 Byte 1 Byte 0 Byte 3 Byte 2 0002 Byte 5 Byte 4 0004 2004 Microchip Technology Inc. ...
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... MSB is always clear. Note push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. 2004 Microchip Technology Inc. 3.2.6 SOFTWARE STACK The dsPIC device contains a software stack. W15 is used as the Stack Pointer. ...
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... The address map shown is conceptual, and may vary across individual devices depending on available memory. DS70082E-page 36 16 bits MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 0x1FFE Y Data RAM (Y) 0x27FE 0x2800 0x8000 X Data Unimplemented (X) 0xFFFE Advance Information LS Byte Address 8 Kbyte Near Data Space 2004 Microchip Technology Inc. ...
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... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA from any W 2004 Microchip Technology Inc. UNUSED Y SPACE UNUSED MAC Class Ops (Read) Indirect EA from W8, W9 Advance Information ...
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... DS70082E-page 38 Advance Information 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. Advance Information dsPIC30F DS70082E-page 39 ...
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... NOTES: DS70082E-page 40 Advance Information 2004 Microchip Technology Inc. ...
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... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. low overhead circular buffers. The X WAGU also sup- ports Bit-Reversed Addressing to facilitate FFT data reorganization ...
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... DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. Advance Information 2004 Microchip Technology Inc. ...
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... Indirect Post-Modification Indirect with Pre- or Indirect with Pre- or Post-Modification Post-Modification 2004 Microchip Technology Inc. 4.3.2 RAW DEPENDENCY DETECTION During the instruction pre-decode, the core determines if any address register dependency is imminent across an instruction boundary. The stall detection logic com- pares the W register (if any) used for the destination EA ...
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... MODCON. Therefore, the instruction immediately following such a POP cannot be any instruction performing an indirect read operation should be noted that some instructions bytes, then the perform an indirect read operation implic- itly. These are: POP, RETURN, RETFIE, RETLW and ULNK. Advance Information 2004 Microchip Technology Inc. ...
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... Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words 2004 Microchip Technology Inc. The X Address Space Pointer W register (XWM) to which modulo addressing applied, is stored in MODCON<3:0> (see Table 3-3). Modulo addressing is enabled for X data space when XWM is set to any value other than 15 and the XMODEN bit is set at MODCON< ...
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... Section 4.4.1). For a decrementing buffer, the circular buffer end address is arbitrary, but must ‘ones’ boundary. There are no restrictions regarding how much an EA calculation can exceed the address boundary being checked and still be successfully corrected. Advance Information 2004 Microchip Technology Inc. ...
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... FIGURE 4-3: BIT-REVERSED ADDRESS EXAMPLE b15 b14 b13 b12 b11 b10 b9 b8 b15 b14 b13 b12 b11 b10 b9 b8 2004 Microchip Technology Inc. of successive 2. the BREN bit is set in the XBREV register and 3. the Addressing mode used is Register Indirect with Pre-Increment or Post-Increment. ...
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... DS70082E-page 48 Decimal XB<14:0> Bit-Reversed Address Modifier Value Advance Information Bit-Reversed Address A0 Decimal 0x4000 0x2000 0x1000 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001 2004 Microchip Technology Inc. ...
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... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit ...
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... OC6 - Output Compare 6 OC7 - Output Compare 7 OC8 - Output Compare 8 INT3 - External Interrupt 3 INT4 - External Interrupt Combined IRQ for CAN2 PWM - PWM Period Match QEI - QEI Interrupt Reserved LVD - Low Voltage Detect FLTA - PWM Fault A FLTB - PWM Fault B Reserved 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. Note that many of these trap conditions can only be detected when they occur. Consequently, the question- able instruction is allowed to complete prior to trap exception processing ...
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... The proces- sor then loads the priority level for this interrupt into the status register. This action will disable all lower priority interrupts until the completion of the Interrupt Service Routine. Advance Information 2004 Microchip Technology Inc. ...
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... Interrupt 1 Vector — — — Interrupt 52 Vector Interrupt 53 Vector 2004 Microchip Technology Inc. 5.5 Alternate Vector Table In Program Memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), as shown in Figure 5-2. Access to the Alternate Vector Table is provided by the ALTIVT bit in the INTCON2 register ...
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... DS70082E-page 54 Advance Information 2004 Microchip Technology Inc. ...
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... Family Reference Manual (DS70046). For complete information on the device instruction set and programming, please refer to the dsPIC30F Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. 6.2 Run Time Self-Programming ...
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... Write address of row to be erased into NVMADRU/NVMDR. c) Write ‘55’ to NVMKEY. d) Write ‘AA’ to NVMKEY. e) Set the WR bit. This will begin erase cycle. f) CPU will stall for the duration of the erase cycle. g) The WR bit is cleared when erase cycle ends. Advance Information 2004 Microchip Technology Inc. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP 2004 Microchip Technology Inc. e) CPU will stall for duration of the program cycle. f) The WR bit is cleared by the hardware when program cycle ends. 6. Repeat steps 1 through 5 as needed to program desired amount of program Flash memory. ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; ; Write PM low word into program latch ; Write PM high byte into program latch Advance Information 2004 Microchip Technology Inc. ...
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... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP 2004 Microchip Technology Inc. ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted ...
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... DS70082E-page 60 Advance Information 2004 Microchip Technology Inc. ...
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... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. Control bit WR initiates write operations, similar to pro- gram Flash writes. This bit cannot be cleared, only set, in software ...
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... Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence Advance Information 2004 Microchip Technology Inc. ...
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... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete 2004 Microchip Technology Inc. The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared; also, the Power-up Timer prevents EEPROM write. The write initiate sequence and the WREN bit together, help prevent an accidental write during brown-out, power glitch or software malfunction. Advance Information 2004 Microchip Technology Inc. ...
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... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. Writes to the latch, write the latch (LATx). Reads from ...
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... ANx pins), may cause the input buffer to consume current that exceeds the device specifications. 1 Output Enable 0 1 Output Data TRIS Latch Data Latch Advance Information will be Output Multiplexers I/O Cell I/O Pad Input Data 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. Advance Information dsPIC30F DS70082E-page 67 ...
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... DS70082E-page 68 Advance Information 2004 Microchip Technology Inc. ...
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... CNEN1 00C0 CN7IE CN6IE CNEN2 00C2 — — CNPU1 00C4 CN7PUE CN6PUE CNPU2 00C6 — — Legend uninitialized bit 2004 Microchip Technology Inc. Bit 13 Bit 12 Bit 11 Bit 10 CN13IE CN12IE CN11IE CN10IE — — — — — — — — Bit 5 ...
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... NOTES: DS70082E-page 70 Advance Information 2004 Microchip Technology Inc. ...
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... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... Low power • Real-Time Clock Interrupts These Operating modes are determined by setting the appropriate bit(s) in the T1CON Control register. FIGURE 9- pF 100K Advance Information RECOMMENDED COMPONENTS FOR TIMER1 LP OSCILLATOR RTC SOSCI 32.768 kHz dsPIC30FXXXX XTAL SOSCO R 2004 Microchip Technology Inc. ...
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... The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. 2004 Microchip Technology Inc. 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective inter- rupt flag, T1IF, is asserted and an interrupt will be gen- erated, if enabled ...
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... DS70082E-page 74 Advance Information 2004 Microchip Technology Inc. ...
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... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. 16-bit Mode: In the 16-bit mode, Timer2 and Timer3 can be configured as two independent 16-bit timers ...
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... Timer configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70082E-page 76 16 TMR2 Sync LSB PR2 Q D TGATE(T2CON<6> TON 1 X Gate 0 1 Sync Advance Information TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 2004 Microchip Technology Inc. ...
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... Equal Comparator x 16 Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK 2004 Microchip Technology Inc. PR2 TMR2 Q D TGATE Gate Sync PR3 Comparator x 16 TMR3 Q D TGATE ...
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... T3IE (IEC0<7>).. Note: In some devices, one or more of the TxCK pins may be absent. For these timers without the external clock input pin, the following modes should not be used: 1. TCS = 1 (16-bit counter) 2. TCS = 0, TGATE = 1 (gated time accumulation. Advance Information 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. Advance Information dsPIC30F DS70082E-page 79 ...
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... NOTES: DS70082E-page 80 Advance Information 2004 Microchip Technology Inc. ...
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... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. The operating modes of the Timer4/5 module are deter- mined by setting the appropriate bit(s) in the 16-bit T4CON and T5CON SFRs ...
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... Reset 0 T5IF Event Flag 1 TGATE T5CK DS70082E-page 82 PR4 TMR4 Q D TGATE Q CK TON 1 X Gate Sync PR5 Comparator x 16 TMR5 Q D TGATE Q CK Sync Advance Information Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. Advance Information dsPIC30F DS70082E-page 83 ...
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... NOTES: DS70082E-page 84 Advance Information 2004 Microchip Technology Inc. ...
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... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. The key operational features of the Input Capture module are: • ...
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... IFSx Status register. Enabling an interrupt is accomplished via the respec- tive capture channel interrupt enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IEC Control register. Advance Information 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. Advance Information dsPIC30F DS70082E-page 87 ...
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... NOTES: DS70082E-page 88 Advance Information 2004 Microchip Technology Inc. ...
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... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. The key operational features of the Output Compare module include: • ...
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... FAULT condition has occurred. This state will be maintained until both of the following events have occurred: • The external FAULT condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits. Advance Information 2004 Microchip Technology Inc. ...
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... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic 0. 2004 Microchip Technology Inc. When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
Page 94
... DS70082E-page 92 Advance Information 2004 Microchip Technology Inc. ...
Page 95
... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. • Three input channels for two phase signals and index pulse • ...
Page 96
... Position counter reset by detection of index pulse, QEIM<2:0> = 110. 2. Position counter reset by match with MAXCNT, QEIM<2:0> = 111. The x4 Measurement mode provides for finer resolu- tion data (more position counts) for determining motor position. Advance Information 2004 Microchip Technology Inc. ...
Page 97
... Timer reg- ister. When UPDN = 1, the timer will count up. When UPDN = 0, the timer will count down. 2004 Microchip Technology Inc. In addition, control bit UPDN_SRC (QEICON<0>) determines whether the timer count direction state is based on the logic state, written into the UPDN control/ status bit (QEICON< ...
Page 98
... The QEIIF bit must be cleared in software. QEIIF is located in the IFS2 Status register. Enabling an interrupt is accomplished via the respec- tive enable bit, QEIIE. The QEIIE bit is located in the IEC2 Control register. Advance Information 2004 Microchip Technology Inc. ...
Page 99
... Microchip Technology Inc. Advance Information dsPIC30F DS70082E-page 97 ...
Page 100
... NOTES: DS70082E-page 98 Advance Information 2004 Microchip Technology Inc. ...
Page 101
... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. • Output override control for Electrically Commutative Motor (ECM) operation • ...
Page 102
... Channel 1 Dead-Time #1 Generator and Override Logic Special Event Postscaler SEVTDIR PTDIR Advance Information PWM4H PWM4L PWM3H Output Generator and PWM3L Override Logic Driver Block PWM2H Generator and PWM2L Override Logic PWM1H PWM1L FLTA FLTB Special Event Trigger 2004 Microchip Technology Inc. ...
Page 103
... PTPER Buffer PTCON Comparator SEVTDIR SEVTCMP PWM time base Note: Details of PWM Generator #1 and #2 not shown for clarity. 2004 Microchip Technology Inc. PWM Enable and Mode SFRs Dead-Time Control SFR FAULT Pin Control SFR PWM Manual Control SFR PWM Generator #3 ...
Page 104
... PWM waveforms can be generated, which are useful for minimizing output waveform distortion in certain motor control applications. Note: Programming a value of 0x0001 in the period register could generate a continu- ous interrupt pulse, and hence, must be avoided. Advance Information 2004 Microchip Technology Inc. ...
Page 105
... If the PWM time base is configured for one of the Up/ Down Count modes, the PWM period will be twice the value provided by Equation 15-1. 2004 Microchip Technology Inc. The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined using Equation 15-2: ...
Page 106
... The two dead-times can be assigned to individual PWM I/O pin pairs. This Operating mode allows the PWM module to drive different transistor/load combinations with each complementary PWM I/O pin pair. Advance Information 2004 Microchip Technology Inc. ...
Page 107
... No dead-time control is implemented between adjacent PWM I/O pins when the module is operating in the Independent mode and both I/O pins are allowed to be active simultaneously. 2004 Microchip Technology Inc. 15.7.3 DEAD-TIME RANGES The amount of dead-time provided by each dead-time unit is selected by specifying the input clock prescaler value and a 6-bit unsigned value ...
Page 108
... A special case exists when a PWM module I/O pair is in the Complementary mode and both pins are pro- grammed to be active on a FAULT condition. The PWMxH pin always has priority in the Complementary mode, so that both I/O pins cannot be driven active simultaneously. Advance Information 2004 Microchip Technology Inc. ...
Page 109
... PTPER. No duty cycle changes or period value changes will have effect while UDIS = 1. 2004 Microchip Technology Inc. 15.14 PWM Special Event Trigger The PWM module has a special event trigger that allows A/D conversions to be synchronized to the PWM time base ...
Page 110
... DS70082E-page 108 Advance Information 2004 Microchip Technology Inc. ...
Page 111
... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. Transmit writes are also double buffered. The user writes to SPIxBUF ...
Page 112
... Edge Control Select Enable Master Clock SDOx SDIy SDIx SDOy LSb Serial Clock SCKx SCKy Advance Information Secondary Primary F CY Prescaler Prescaler 1,2,4,6 16, 64 SPI Slave Serial Input Buffer (SPIyBUF) Shift Register (SPIySR) MSb LSb PROCESSOR 2 2004 Microchip Technology Inc. ...
Page 113
... Therefore, when the SSx pin is asserted low again, transmission/reception will begin at the MS bit, even if SSx had been de-asserted in the middle of a transmit/receive. 2004 Microchip Technology Inc. 16.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut-down. If ...
Page 114
... DS70082E-page 112 Advance Information 2004 Microchip Technology Inc. ...
Page 115
... Family Reference Manual (DS70046). For complete information on the device instruction set and programming, please refer to the dsPIC30F Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. 17.1 Operating Function Description ...
Page 116
... I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F OSC Advance Information Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read 2004 Microchip Technology Inc. ...
Page 117
... I2CRCV is not full or I2COV is not set, I2CRSR is transferred to I2CRCV. ACK is sent on the ninth clock. 2004 Microchip Technology Inc. If the RBF flag is set, indicating that I2CRCV is still holding data from a previous operation (RBF = 1), then ACK is not sent; however, the interrupt pulse is gener- ated ...
Page 118
... C Master Interrupt Flag) and SI2CIF (I rupt Flag). The MI2CIF interrupt flag is activated on completion of a master message event. The SI2CIF interrupt flag is activated on detection of a message directed to the slave. Advance Information 2 C bus have de-asserted SCL Slave Inter- 2004 Microchip Technology Inc. ...
Page 119
... The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start 2004 Microchip Technology Inc. condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I not be released ...
Page 120
... MODE 2 For the I C, the I2CSIDL bit selects if the module will stop on Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle. Advance Information 2 C bus is free 2004 Microchip Technology Inc. ...
Page 121
... Microchip Technology Inc. Advance Information dsPIC30F DS70082E-page 119 ...
Page 122
... NOTES: DS70082E-page 120 Advance Information 2004 Microchip Technology Inc. ...
Page 123
... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. • Fully integrated Baud Rate Generator with 16-bit prescaler • ...
Page 124
... Generate Flags – Generate Interrupt – Shift Data Characters 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16X Baud Clock from Baud Rate Generator Advance Information Read Read Write UxMODE UxSTA Control Signals UxRXIF 2004 Microchip Technology Inc. ...
Page 125
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (Power-on) setting of the UART is 8 bits, no parity, 1 Stop bit (typically represented 1). 2004 Microchip Technology Inc. 18.3 Transmitting Data 18.3.1 TRANSMITTING IN 8-BIT DATA ...
Page 126
... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. Advance Information RXB) X 2004 Microchip Technology Inc. ...
Page 127
... No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not been received yet. 2004 Microchip Technology Inc. 18.6 Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables this spe- cial mode, in which a 9th bit (URX8) value of ‘ ...
Page 128
... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode, or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. Advance Information 2004 Microchip Technology Inc. ...
Page 129
... Microchip Technology Inc. Advance Information dsPIC30F DS70082E-page 127 ...
Page 130
... NOTES: DS70082E-page 128 Advance Information 2004 Microchip Technology Inc. ...
Page 131
... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. The CAN bus module consists of a protocol engine, and message buffering/control ...
Page 132
... RXF2 A Acceptance Filter c RXF3 c Acceptance Filter e RXF4 p t Acceptance Filter RXF5 R M Identifier Data Field Receive RERRCNT Error Counter TERRCNT Transmit ErrPas Error BusOff Counter Protocol Finite State Machine Bit Timing Bit Timing Logic Generator (1) CiRX 2004 Microchip Technology Inc. ...
Page 133
... The I/O pins will revert to normal I/O function when the module is in the module disable mode. 2004 Microchip Technology Inc. The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...
Page 134
... These receive errors do not generate an interrupt. However, the receive error counter is incremented by one in case one of these errors occur. The RXWAR bit (CiINTF<9>) indicates that the Receive Error Counter has reached the CPU warning limit of 96 and an interrupt is generated. Advance Information 2004 Microchip Technology Inc. ...
Page 135
... If TXPRI<1:0> for a particular message buffer is set to ‘10’ or ‘01’, that buffer has an intermediate priority. If TXPRI<1:0> for a particular message buffer is ‘00’, that buffer has the lowest priority. 2004 Microchip Technology Inc. 19.5.3 TRANSMISSION SEQUENCE To initiate transmission of the message, the TXREQ bit (CiTXnCON< ...
Page 136
... definition, the Nominal Bit Time has a minimum and a maximum the minimum nominal bit time is 1 µsec, corresponding to a maximum bit rate of 1 MHz. Phase Segment 1 Segment 2 Sample Point Advance Information Q . Also, by definition, Phase Sync 2004 Microchip Technology Inc. ...
Page 137
... SAM bit (CiCFG2<6>). Typically, the sampling of the bit should take place at about 60-70% through the bit time, depending on the system parameters. 2004 Microchip Technology Inc. 19.6.6 SYNCHRONIZATION To compensate for phase shifts between the oscillator frequencies of the different bus stations, each CAN ...
Page 138
... DS70082E-page 136 Advance Information 2004 Microchip Technology Inc. ...
Page 139
... Microchip Technology Inc. Advance Information dsPIC30F DS70082E-page 137 ...
Page 140
... DS70082E-page 138 Advance Information 2004 Microchip Technology Inc. ...
Page 141
... Microchip Technology Inc. Advance Information dsPIC30F DS70082E-page 139 ...
Page 142
... NOTES: DS70082E-page 140 Advance Information 2004 Microchip Technology Inc. ...
Page 143
... Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. The A/D module has six 16-bit registers: • A/D Control Register1 (ADCON1) • ...
Page 144
... Note: Input multiplexer circuit will vary depending on the device selected. DS70082E-page 142 CH1 ADC S/H - 10-bit Result + CH2 S CH3 S/H CH1,CH2, - CH3,CH0 sample input switches + CH0 S/H - Advance Information Conversion Logic 16-word, 10-bit Dual Port Buffer Sample/Sequence Control Input Mux Control 2004 Microchip Technology Inc. ...
Page 145
... The channels are then converted sequentially. Obvi- ously, if there is only 1 channel selected, the SIMSAM bit is not applicable. 2004 Microchip Technology Inc. The CHPS bits selects how many channels are sam- pled. This can vary from channels. If CHPS selects 1 channel, the CH0 channel will be sampled at the sample clock and converted ...
Page 146
... MHz 1 MHz (2) ( 500 ns (2) 1.0 µs 160 ns (3) 2.0 µs 320 ns (3) (3) 4.0 µs 640 ns (3) (3) (3) 1.28 µs 8.0 µs (3) (3) (3) 2.56 µs 16.0 µs (3) (3) (3) 5.12 µs 32.0 µs (1,4) (1,4) (1) 200-400 ns 200-400 ns 2004 Microchip Technology Inc. ...
Page 147
... Integer 0 2004 Microchip Technology Inc. If the A/D interrupt is enabled, the device will wake-up from Sleep. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set ...
Page 148
... Any external components connected (via high impedance analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. Advance Information DD SS and V as ESD the input voltage exceeds this 2004 Microchip Technology Inc. ...
Page 149
... Microchip Technology Inc. Advance Information dsPIC30F DS70082E-page 147 ...
Page 150
... NOTES: DS70082E-page 148 Advance Information 2004 Microchip Technology Inc. ...
Page 151
... Family Reference Manual (DS70046). For complete information on the device instruction set and programming, please refer to the dsPIC30F Programmer’s Reference Manual (DS70030). For device pinouts and electrical specifications, please refer to the specific data sheet for the device that will be used in your design. 2004 Microchip Technology Inc. 21.1 Oscillator System Overview ...
Page 152
... LP oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation MHz. 4: Some dsPIC30F devices do not have these oscillator options. Please refer to the specific device data sheet for details. DS70082E-page 150 Description (1) (2) (3) OSC /4 output (3) (4) (4) (4) Advance Information (1) (1) (1) 2004 Microchip Technology Inc. ...
Page 153
... OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI . Note: Paths indicated by dotted lines are not available on all devices. Please refer to the specific device data sheet for details. 2004 Microchip Technology Inc. PLL F PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator ...
Page 154
... Note: When a 16x PLL is used, the FRC frequency must not be tuned to a frequency greater than 7.5 MHz. Advance Information PLL FREQUENCY RANGE PLL Fout Multiplier x4 16 MHz-40 MHz x8 32 MHz-80 MHz x16 64 MHz-160 MHz 2004 Microchip Technology Inc. ...
Page 155
... Note that OSC1 pin cannot be used as an I/O pin, even if the secondary oscillator or an internal clock source is selected at all times. 2004 Microchip Technology Inc. 21.2.7 FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure ...
Page 156
... Byte Write “0x78” to OSCCON high • Byte Write “0x9A” to OSCCON high Byte Write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. Advance Information 2004 Microchip Technology Inc. ...
Page 157
... Reset state. The POR also selects the device clock source identified by the oscil- lator configuration fuses. 2004 Microchip Technology Inc. Different registers are affected in different ways by var- ious Reset conditions. Most registers are not affected by a WDT wake-up, since this is viewed as the resump- tion of normal operation ...
Page 158
... OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset DS70082E-page 156 T OST T PWRT T OST PWRT T OST T PWRT T Advance Information ) DD ): CASE CASE 2 DD 2004 Microchip Technology Inc. ...
Page 159
... The BOR voltage trip points indicated here are nominal values provided for design guidance only. 2004 Microchip Technology Inc. A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source, based on the device configuration bit values (FOS<1:0> and FPR< ...
Page 160
... When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70082E-page 158 TRAPR IOPUWR EXTR SWR WDTO ( TRAPR IOPUWR EXTR SWR WDTO ( Advance Information Idle Sleep POR BOR Idle Sleep POR BOR 2004 Microchip Technology Inc. ...
Page 161
... In some devices, the LVD threshold voltage may be applied externally on the LVDIN pin. The LVD module is enabled by setting the LVDEN bit (RCON<12>). 2004 Microchip Technology Inc. 21.6 Power Saving Modes There are two power saving states that can be entered through the execution of a special instruction, PWRSAV. ...
Page 162
... For additional information, please specifications of the device. Note: If the code protection configuration fuse bits (FGS<GCP> and FGS<GWRP>) have been programmed, an erase of the entire code-protected device is only possible at voltages V Advance Information refer to the programming ≥ 4.5V. DD 2004 Microchip Technology Inc. ...
Page 163
... To use the In-Circuit Debugger function of the device, the design must implement ICSP connections to MCLR, V PGC, PGD, and the selected EMUDx/EMUCx pin pair. 2004 Microchip Technology Inc. This gives rise to two possibilities EMUD/EMUC is selected as the Debug I/O pin ...
Page 164
... DS70082E-page 162 Advance Information 2004 Microchip Technology Inc. ...
Page 165
... A literal value to be loaded into a W register or file register (specified by the value of ’k’) • The W register or file register where the literal value loaded (specified by ’Wb’ or ’f’) 2004 Microchip Technology Inc. However, literal instructions that involve arithmetic or logical operations use some of the following operands: adds many • ...
Page 166
... Wm*Wn {W4*W5,W4*W6,W4*W7,W5*W6,W5*W7,W6*W7} One of 16 working registers ∈ {W0..W15} Wn One of 16 destination working registers ∈ {W0..W15} Wnd One of 16 source working registers ∈ {W0..W15} Wns W0 (working register used in file register instructions) WREG DS70082E-page 164 Description Advance Information 2004 Microchip Technology Inc. ...
Page 167
... Y data space pre-fetch address register for DSP instructions Wy ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space pre-fetch destination register for DSP instructions ∈ {W4..W7} Wyd 2004 Microchip Technology Inc. Description Advance Information dsPIC30F DS70082E-page 165 ...
Page 168
... None 1 1 (2) None 1 1 (2) None 1 1 (2) None 1 1 (2) None 1 1 (2) None 1 1 (2) None 1 1 (2) None 1 2 None 1 1 (2) None 1 2 None 1 1 None 1 1 None 1 1 None 1 1 None 1 1 None 1 1 None 1 1 None ( None ( 2004 Microchip Technology Inc. ...
Page 169
... Wm, #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 2004 Microchip Technology Inc. Description Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws<Wb> Bit Test then Set f Bit Test then Set Bit Test then Set ...
Page 170
... None 1 1 None 1 1 None None 1 2 None 1 1 None 1 1 OA,OB,OAB, SA,SB,SAB 1 1 OA,OB,OAB, SA,SB,SAB 1 1 None 1 1 OA,OB,OAB, SA,SB,SAB 1 1 None 1 1 None 1 1 None 1 1 None 1 1 None 1 1 None 1 1 None 2004 Microchip Technology Inc. ...
Page 171
... SFTAC Acc,#Slit6 f,WREG SL Ws,Wd SL Wb,Wns,Wnd SL Wb,#lit5,Wnd 2004 Microchip Technology Inc. Description Negate Accumulator WREG = Operation No Operation Pop f from top-of-stack (TOS) Pop from top-of-stack (TOS) to Wdo Pop from top-of-stack (TOS) to W(nd):W(nd+1) Pop Shadow Registers Push f to top-of-stack (TOS) ...
Page 172
... C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV C,DC,N,OV None 1 1 None 1 2 None 1 2 None 1 2 None 1 2 None 1 1 None C,Z,N 2004 Microchip Technology Inc. ...
Page 173
... PICDEM MSC ® - microID - CAN ® - PowerSmart - Analog 2004 Microchip Technology Inc. 23.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...
Page 174
... MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high speed simulator is designed to debug, analyze and optimize time intensive DSP routines. Advance Information excellent, economical software 2004 Microchip Technology Inc. ...
Page 175
... The PC platform and Microsoft Windows 32-bit operating system were cho- sen to best make these features available in a simple, unified application. 2004 Microchip Technology Inc. 23.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low cost, run-time development tool, connecting to the host PC via an RS-232 or high speed USB interface ...
Page 176
... PICSTART Plus development pro- grammer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board FLASH memory. A generous prototype area is available for user hardware expansion. Advance Information 2004 Microchip Technology Inc. ...
Page 177
... Microcontrollers" Handbook and a USB Interface Cable. Supports all current 8/14-pin FLASH PIC microcontrollers, as well as many future planned devices. 2004 Microchip Technology Inc. 23.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...
Page 178
... NOTES: DS70082E-page 176 Advance Information 2004 Microchip Technology Inc. ...
Page 179
... Exposure to maximum rating conditions for extended periods may affect device reliability. Note: All peripheral electrical characteristics are specified. For exact peripherals available on specific devices, please refer the the Family Cross Reference Table. 2004 Microchip Technology Inc. DD (except V and MCLR) ................................................... -0. (Note 1) ...
Page 180
... RAM data. Advance Information dsPIC30FXXX-20E 7.5 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Units Conditions V Industrial temperature V Extended temperature V V V/ms 0-5V in 0.1 sec 0- 2004 Microchip Technology Inc. ...
Page 181
... WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory are operational. No peripheral modules are operating. 3: Data is provided for the dsPIC30F6010 device. Other devices will have different I specific device data sheet for details. 2004 Microchip Technology Inc Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 182
... DD measurements are as follows: OSC1 Advance Information 10 MIPS EC mode, 4X PLL 8 MIPS EC mode, 8X PLL 15 MIPS EC mode, 8X PLL 20 MIPS EC mode, 8X PLL values. Refer to the 2004 Microchip Technology Inc. ...
Page 183
... WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory are operational. No peripheral modules are operating. 3: Data is provided for the dsPIC30F6010 device. Other devices will have different I specific device data sheet for details. 2004 Microchip Technology Inc. ) (CONTINUED) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 184
... Advance Information 1 MIPS EC mode 2.5 MIPS EC mode 10 MIPS EC mode 4 MIPS EC mode, 4X PLL DD values. Refer to the 2004 Microchip Technology Inc. ...
Page 185
... Core off, Clock on and all modules turned off. 3: Data is provided for the dsPIC30F6010 device. Other devices will have different I specific device data sheet for details. 2004 Microchip Technology Inc. ) (CONTINUED) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 186
... V mA 85°C mA 125°C Advance Information 16 MIPS EC mode, 16X PLL 30 MIPS EC mode, 16X PLL FRC (~ 2 MIPS) LPRC (~ 512 kHz) DD values. Refer to the 2004 Microchip Technology Inc. ...
Page 187
... LVD, BOR, WDT, etc. are all switched off. The ∆ current is the additional current consumed when the module is enabled. This current should added to the base I current. 2004 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial A Operating temperature -40° ...
Page 188
... Advance Information ) (CONTINUED) PD (3) 10-bit ADC: ∆I ADC 10 (3) 12-bit ADC: ∆I ADC 12 (3) Low Voltage Detect: ∆I LVD 2004 Microchip Technology Inc. ...
Page 189
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. 2004 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
Page 190
... Advance Information ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions 8.5 mA 2.0 mA 1.6 mA 2.0 mA -3.0 mA -2.0 mA -1.3 mA -2.0 mA XTL, XT, HS and LP modes when external clock is used to drive OSC1 Osc mode mode 2004 Microchip Technology Inc. ...
Page 191
... These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. FIGURE 24-2: BROWN-OUT RESET CHARACTERISTICS DD V BO10 (Device in Brown-out Reset) RESET (due to BOR) 2004 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min (2) DD transition LVDL = 0000 — ...
Page 192
... Industrial A ≤ +125°C for Extended A Conditions -40°C ≤ T ≤ +85° Using EECON to read/write MIN V = Minimum operating voltage ms are violated Row Erase -40°C ≤ T ≤ +85°C A MIN Minimum operating voltage are violated ms Row Erase Bulk Erase 2004 Microchip Technology Inc. ...
Page 193
... LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Pin FIGURE 24-4: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT 2004 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ Operating voltage V range as described in DC Spec Section 24.0. Load Condition 2 – ...
Page 194
... XT with 16x PLL MHz HS kHz LP MHz FRC internal kHz LPRC internal — See parameter OS10 for OSC F value ns See Table 24-14 ns XTL osc ns XT osc µs LP osc ns HS osc ns XTL osc ns XT osc ns LP osc ns HS osc 2004 Microchip Technology Inc. ...
Page 195
... F21 Note 1: Frequency calibrated at 25°C. TUN bits can be used to compensate for temperature drift. 2: LPRC frequency after calibration. 3: Change of LPRC frequency as V 2004 Microchip Technology Inc. = 2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ Operating temperature -40° ...
Page 196
... T A Operating temperature -40°C ≤ (1)(2)(3) (4) Min Typ — 10 — — — Advance Information ≤ +85°C for Industrial ≤ +125°C for Extended Max Units Conditions 25 ns — — — ns — — ns — OSC . 2004 Microchip Technology Inc. ...
Page 197
... SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins SY35 FSCM Delay Note: Refer to Figure 24-3 for load conditions. 2004 Microchip Technology Inc. SY10 SY13 Advance Information dsPIC30F SY20 SY13 DS70082E-page 195 ...
Page 198
... Band Gap Stable ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. RCON<13>Status bit 2004 Microchip Technology Inc. ...
Page 199
... TCS (T1CON, bit 1)) CKEXTMRL TA20 T Delay from External TQCK Clock Edge to Timer Increment Note: Timer1 is a Type A. 2004 Microchip Technology Inc. Tx1 Tx1 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 200
... OSC 6 T — ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions — ns Must also meet parameter TC15 — ns Must also meet parameter TC15 — prescale value (1, 8, 64, 256) OSC 6 T — 2004 Microchip Technology Inc. ...