STA326 STMicroelectronics, STA326 Datasheet

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STA326

Manufacturer Part Number
STA326
Description
DIG AUDIO SYSTEM, 2-CH, 36POWERSSOP
Manufacturer
STMicroelectronics
Datasheet

Specifications of STA326

Svhc
No SVHC (15-Dec-2010)
No. Of Pins
36
Operating Temperature Range
-20°C To +85°C
Supply Voltage Max
36V
Supply Voltage Min
10V
Termination T
RoHS Compliant
Package / Case
PowerSO
Interface
I2C
Interface Type
I2C
Rohs Compliant
Yes

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Features
Table 1.
November 2010
STA326
STA32613TR
Wide supply voltage range (10 V - 36 V)
Three power output configurations
– 2 x 40 W + 1 x 80 W
– 2 x 80 W
– 1 x 160 W
PowerSO-36 package (exposed pad up (EPU))
2.1 channels of 24-bit DDX
100-dB SNR and dynamic range
32 kHz to 192 kHz input sample rates
Digital gain/attenuation +48 dB to -80 dB in
0.5-dB steps
Four 28-bit user programmable biquads (EQ)
per channel
I
2-channel I
Individual channel and master gain/attenuation
Individual channel and master soft/hard mute
Individual channel volume and EQ bypass
Bass/treble tone control
Dual independent programmable
limiters/compressors
Automodes
– 32 preset EQ curves
– 15 preset crossover settings
– Auto volume controlled loudness
– 3 preset volume curves
2
C control
Order code
Device summary
2
S input data interface
®
2.1-channel high-efficiency digital audio system
PowerSO-36 EPU
PowerSO-36 EPU
Doc ID 11531 Rev 3
Package
– 2 preset anti-clipping modes
– Preset night-time listening mode
– Preset TV AGC
Input and output channel mapping
AM noise-reduction and PWM
frequency-shifting modes
Software volume update and muting
Auto zero detect and invalid input detect
muting
Selectable DDX
output + variable PWM speeds
Selectable de-emphasis
Post-EQ user programmable mix with default
2.1 bass-management settings
Variable max power correction for lower full-
power THD
Four output routing configurations
Selectable clock input ratio
96 kHz internal processing sample rate, 24 to
28-bit precision
Video application supports 576 * fs input mode
Tube
Tape and reel
®
ternary or binary PWM
PowerSO-36
with exposed pad up
Packaging
STA326
www.st.com
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STA326 Summary of contents

Page 1

... Four output routing configurations Selectable clock input ratio 96 kHz internal processing sample rate 28-bit precision Video application supports 576 * fs input mode Package PowerSO-36 EPU PowerSO-36 EPU Doc ID 11531 Rev 3 STA326 PowerSO-36 with exposed pad up ® ternary or binary PWM Packaging Tube Tape and reel www.st.com ...

Page 2

... Configuration register C (addr 0x02 6.3.1 6.3.2 6.4 Configuration register D (addr 0x03 6.5 Configuration register E (addr 0x04 6.6 Configuration register F (addr 0x05 6.7 Volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.7.1 2/57 ® DDX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ® DDX variable compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . 25 Master controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Doc ID 11531 Rev 3 STA326 ...

Page 3

... STA326 6.7.2 6.7.3 6.8 Automode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.8.1 6.8.2 6.8.3 6.9 Channel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.9.1 6.9.2 6.9.3 6.10 Tone control (addr 0x11 6.11 Dynamics control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.11.1 6.11.2 6.11.3 6.11.4 6.11.5 6.11.6 6.11.7 7 User programmable processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7 biquad equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.2 Prescale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.3 Postscale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7 ...

Page 4

... Coefficient a2 data register bits 15:8 (addr 0x21 Coefficient a2 data register bits 7:0 (addr 0x22 Coefficient b0 data register bits 23:16 (addr 0x23 Coefficient b0 data register bits 15:8 (addr 0x24 Coefficient b0 data register bits 7:0 (addr 0x25 Coefficient write control register (addr 0x26 Doc ID 11531 Rev 3 STA326 ...

Page 5

... The IC can also be configured as a single parallel full-bridge capable of high-current operation and 1 x 160 W output. Also provided in the STA326 is a full assortment of digital processing features. This includes up to four programmable 28-bit biquads (EQ) per channel and bass/treble tone control. Automodes enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions ...

Page 6

... Doc ID 11531 Rev 3 De- Bass T reble BQ#4 Emphasis Filter Filter T o Mix If CxT Bass Boost/Cut If DEMP = reble Boost/Cut 2-channel (full-bridge) configuration, register bits OCFG[1: 2.1-channel configuration, register bits OCFG[1: 1-channel mono-parallel configuration, register bits OCFG[1: The setup register is Configuration register F (addr 0x05) on page 30 STA326 ...

Page 7

... STA326 2 Pin out 2.1 Package pins Figure 5. Pin connections 2.2 Pin list Table 2. Pin list Number 1 I I/O 5 N.C. 6 I/O 7 I I/O 12 I/O 13 I/O. 14 N.C. VCC_SIGN 36 VSS 35 VDD 34 GND 33 BICKI 32 LRCKI 31 SDI 30 VDDA 29 GNDA 28 XTI 27 PLL_FILTER 26 RESERVED 25 SDA 24 SCL ...

Page 8

... SDI I LRCKI I BICKI I GND Digital ground VDD Digital supply, nominally 3.3 V VSS 5 V regulator referred to +V VCC_SIGN 5 V regulator referred to ground Doc ID 11531 Rev 3 Description 2 C serial clock 2 C serial data 2 S serial data channels 1 & left/right clock serial clock CC STA326 ...

Page 9

... STA326 2.3 Pin description OUT1A, 1B, 2A and 2B (pins 16, 10, 9 and 3) Output half bridge PWM outputs 1A, 1B, 2A and 2B provide the input signals to the speakers. RESET (pin 22) Driving RESET low sets all outputs low and returns all register settings to their default (reset) values. The reset is asynchronous to the internal clock. ...

Page 10

... Value -0 -0 0.5) DD33 -0 0.5) DD33 -40 to +150 -20 to +85 40 5.5 Min Typ Max - - 2.5 - 150 - - 130 - - 25 - Value 3.0 to 3.6 -20 to +125 Min. Typ. Max ( ( 2000 - - STA326 Unit °C ° Unit °C/W °C °C °C Unit V °C Unit µA µA µA V ...

Page 11

... STA326 3.2 DC electrical specifications (3.3 V buffers) Operating conditions V Table 7. DC electrical specifications Symbol V Low level input voltage IL V High level input voltage IH V Schmitt trigger hysteresis hyst V Low level output ol V High level output oh 3.3 Power electrical specifications Operating conditions V otherwise specified. ...

Page 12

... Duty cycle A and B: Fixed to have DC output current the direction shown in figure Doc ID 11531 Rev 3 Min. Typ. Max 4 150 = OUTxY Vcc (3/4)Vcc (1/2)Vcc (1/4)Vcc t DTr DTf V67 - vdc = Vcc/2 Duty cycle=B M64 Q2 DTout(B) OUTB L68 10µ Iout=1.5A M63 C70 Q4 470nF D06AU1651 STA326 Unit DTin(B) INB ...

Page 13

... STA326 4 Characterization curves Figure 8. Channel separation vs frequency dBr A dBr A Figure 9. THD vs output power - single ended THD (%) THD (%) +10 + -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 -80 -80 -90 - 100 100 200 200 500 500 Vcc = 36 V Vcc = Ω Ω kHz kHz 0.5 0.5 ...

Page 14

... Vcc = 36 V Vcc = Ω Ω 0.2 0 kHz kHz 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0. 100 100 200 200 Doc ID 11531 Rev 100 100 Po (W) Po (W) 500 500 10k 10k 20k 20k Hz Hz STA326 ...

Page 15

... STA326 and the bus master. Data input During the data input the STA326 samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. ...

Page 16

... START Current address byte read Following the START condition the master sends a device select code with the RW bit set to 1. The STA326 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition. 16/57 ...

Page 17

... After receiving, the internal byte address the STA326 again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA326 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition ...

Page 18

... C1B19 C1B18 C1B17 C1B11 C1B10 C1B9 C1B3 C1B2 C1B1 C2B19 C2B18 C2B17 C2B11 C2B10 C2B9 C2B3 C2B2 C2B1 C3B19 C3B18 C3B17 STA326 D0 MCS0 SAI0 OM0 HPB MPCV OCFG0 MMUTE MV0 C1V0 C2V0 C3V0 AMEQ0 AMAME PEQ0 C1TCB C2TCB Reserved BTC0 L1R0 ...

Page 19

... RW 0 The STA326 will support sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. Therefore the internal clock will be: 32.768 MHz for 32 kHz 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs) ...

Page 20

... R/W RST 4 The STA326 has variable interpolation (re-sampling) settings such that internal processing ® and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a down-sample by a factor of 2. The IR bits determine the re-sampling ratio of this interpolation. ...

Page 21

... RW 1 The on-chip STA326 power output block provides feedback to the digital controller using inputs to the power control block. The TWARN input is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period greater than 400 ms, the power control block will force an adjustment to the modulation limit in an attempt to eliminate the thermal warning condition ...

Page 22

... The STA326 serial audio input was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA326 always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI (pin 31), serial clock BICKI (pin 32), and serial data SDI (pin 30) ...

Page 23

... STA326 Table 18. Supported serial audio input formats BICKI SAI [3: 1100 1110 0100 0100 1000 0100 1100 0001 0101 1001 1101 0010 0110 1010 1110 0000 0100 1000 0000 1100 0001 0101 1001 1101 0010 0110 1010 1110 For example, SAI = 1110 and SAIFB = 1 would specify right-justified 16-bit data, LSB-first. ...

Page 24

... S can be mapped to any internal processing channel via the 2 S input channel to its corresponding processing channel. Doc ID 11531 Rev 3 Value 12.5 MHz max min min min min min min Description 2 S master devices Description 2 S input 2 S input 2 S input 2 S input STA326 ...

Page 25

... STA326 6.3 Configuration register C (addr 0x02) D7 Reserved CSZ4 0 ® 6.3.1 DDX power output mode Table 22. DDX Bit R/W RST 1 ® The DDX power output mode selects how the DDX power devices can use different output modes. The recommended use 10. When the CSZ bits determine the size of the DDX Table 23 ...

Page 26

... Table 25. High-pass filter bypass Bit R/W RST The STA326 features an internal digital high-pass filter for the purpose of DC Blocking. The purpose of this filter is to prevent DC signals from passing through a DDX signals can cause speaker damage. Table 26. De-emphasis Bit R/W RST setting this bit to 1, the de-emphasis will be implemented on all channels ...

Page 27

... STA326 Table 29. Biquad coefficient link Bit R/W RST For ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once. Table 30. Dynamic range compression/anti-clipping bit ...

Page 28

... RST The STA326 features a DDX generated in the frequency range of AM radio. This mode is intended for use when DDX operating in a device with an active AM tuner. The SNR of the DDX to approximately this mode, which is still greater than the SNR of AM radio. Table 36. ...

Page 29

... RW 1 The STA326 includes a soft volume algorithm that will step through the intermediate volume values at a predetermined rate when a volume change occurs. By setting SVE = 0 this can be bypassed and volume changes will jump from old to new value directly. This feature is only available if individual channel volume bypass bit is set to 0. ...

Page 30

... Name Invalid input detect auto-mute enable: IDE 0: disabled 1: enabled Name Binary output mode clock loss detection enable BCLE 0: disabled 1: enabled Doc ID 11531 Rev BCLE IDE OCFG1 Description ® DDX : Description 2 S data and clocking and Description STA326 D0 OCFG0 0 ® DDX is ...

Page 31

... STA326 Table 43. Auto-EAPD on clock loss enable Bit R/W RST When ECLE is active, it issues a power device power down signal (EAPD) on clock loss detection. Table 44. Software power down Bit R/W RST Table 45. External amplifier power down Bit R/W RST EAPD is used to actively power down a connected DDX ...

Page 32

... Volume description The volume structure of the STA326 consists of individual volume registers for each of the three channels and a master volume register, and individual channel volume trim registers. The channel volume settings are normally used to set the maximum allowable digital gain and to hard-set gain differences between certain channels. These values are normally set at the initialization of the IC and not changed ...

Page 33

... When ZCE = 0, volume updates will occur immediately. The STA326 also features a soft-volume update function that will ramp the volume between intermediate values when the value is updated, when SVE = 1 (configuration register E). ...

Page 34

... MVOL auto curve 50 steps User programmable clipping AC limited clipping (10%) DRC nighttime listening mode Name Automode prescale AMPS 0: -18 dB used for prescale when AMEQ neq 00 1: user defined prescale when AMEQ neq 00 Doc ID 11531 Rev 3 STA326 D2 D1 AMV0 AMEQ1 AMEQ0 0 0 Mode (MVOL) Mode Description ...

Page 35

... STA326 6.8.2 Automode AM/prescale/bass management scale (addr 0x0C XO3 XO2 0 0 Table 52. Automode AM switching enable Bit R/W RST 3:1 RW 000 n Table 53. Automode AM switching frequency selection AMAM[2:0] 000 001 010 011 100 101 110 ® When DDX is used concurrently with an AM radio tuner advisable to use the AMAM bits to automatically adjust the output PWM switching rate dependent upon the specific radio frequency that the tuner is receiving ...

Page 36

... Hz 200 Hz 220 Hz 240 Hz 260 Hz 280 Hz 300 Hz 320 Hz 340 Hz 360 Reserved PEQ4 PEQ3 Setting Flat Rock Soft rock Jazz Classical Dance Pop Soft Hard Party Vocal Hip-hop Dialog Bass-boost #1 Bass-boost #2 Bass-boost #3 Loudness 1 (least boost) Doc ID 11531 Rev 3 STA326 PEQ2 PEQ1 PEQ0 ...

Page 37

... STA326 Table 56. Preset EQ selection (continued) PEQ[3:0] 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 6.9 Channel configuration registers 6.9.1 Channel 1 configuration (addr 0x0E) D7 C1OM1 C1OM0 0 6.9.2 Channel 2 configuration (addr 0x0F C2OM1 C2OM0 0 0 6.9.3 ...

Page 38

... PWM encoded data. By setting the CxBO bit to 1, each channel can be individually controlled binary operation mode. Also, there is the capability to map each channel independently onto any of the two limiters available within the STA326 or even not map it to any limiter at all (default mode). Table 57. Channel limiter mapping selection ...

Page 39

... STA326 6.10 Tone control (addr 0x11 TTC3 TTC2 0 1 Table 59. Tone control boost/cut selection BTC[3:0]/TTC[3:0] 0000 0001 … 0111 0110 0111 1000 1001 … 1101 1110 1111 TTC1 TTC0 BTC3 -12 dB -12 dB … … +12 dB +12 dB +12 dB Doc ID 11531 Rev 3 ...

Page 40

... Dynamics control description The STA326 includes 2 independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode actively reduce the dynamic range for a better listening environment (such as a night-time listening mode, which is often needed for DVDs.) The two modes are selected via the DRC bit in configuration register D (bit 5, address 0x03) ...

Page 41

... STA326 and therefore the release will only occur if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range. This is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless”. ...

Page 42

... Attack threshold (AC) dB relative to FS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Doc ID 11531 Rev 3 Release threshold (AC) LxRT[3:0] dB relative to FS -∞ -29 dB -20 dB -16 dB -14 dB - STA326 ...

Page 43

... STA326 6.11.7 Dynamic range compression mode Table 62. Limiter attack/release threshold selection (DRC mode) LxAT[3:0] 0000 -31 0001 -29 0010 -27 0011 -25 0100 -23 0101 -21 0110 -19 0111 -17 1000 -16 1001 -15 1010 -14 1011 -13 1100 -12 1101 -10 1110 -7 1111 -4 Attack threshold (DRC) dB relative to volume Doc ID 11531 Rev 3 Register description Release threshold (DRC) ...

Page 44

... Postscale The STA326 provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. This is a 24-bit signed fractional multiplier. The scale factor for this multiplier is loaded into RAM using the same I as the biquad coefficients and the mix. All channels can use the same settings as channel 1 by setting the postscale link bit ...

Page 45

... STA326 7.4 Mix/bass management The STA326 provides a post EQ mixing block per channel. Each channel has 2 mixing coefficients, which are each 24-bit signed fractional multipliers, that correspond to the 2 channels of input to the mixing block. These coefficients are accessible via the user controlled coefficient RAM described below. The mix coefficients are expressed as 24-bit signed ...

Page 46

... Calculating 24-bit signed fractional numbers from a dB value The prescale, mixing, and postscale functions of the STA326 use 24-bit signed fractional multipliers to attenuate signals. These attenuations can also invert the phase and therefore range in value from - possible to calculate the coefficient to utilize for a given negative dB value (attenuation) via the equations below ...

Page 47

... STA326 7.6.6 Coefficient b2 data register bits 15:8 (addr 0x1B C2B15 C2B14 0 7.6.7 Coefficient b2 data register bits 7:0 (addr 0x1C C2B7 C2B6 0 7.6.8 Coefficient a1 data register bits 23:16 (addr 0x1D C1B23 C1B22 0 0 7.6.9 Coefficient a1 data register bits 15:8 (addr 0x1E C3B15 ...

Page 48

... Reserved Reserved 0 Coefficients for EQ, mix and scaling are handled internally in the STA326 via RAM. Access to this RAM is available to the user via an I are dedicated to this function. First register contains the coefficient base address, five sets of three registers store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the read or write of the coefficient (s) to RAM ...

Page 49

... STA326 7.7 Reading a coefficient from RAM write 8 bits of address to I write 1 to bit R1 (D2 read top 8 bits of coefficient in I read middle 8 bits of coefficient in I read bottom 8 bits of coefficient in I 7.8 Reading a set of coefficients from RAM write 8 bits of address to I write 1 to bit RA (D3 ...

Page 50

... When using this technique, the 8-bit address would specify the address of the biquad b1 coefficient (for example 0, 5, 10, 15, …, 45 decimal), and the STA326 will generate the RAM addresses as offsets from this base value to write the complete set of coefficient data. ...

Page 51

... STA326 Table 63. RAM block for biquads, mixing, and scaling (continued) Index (decimal Index (Hex) Description 0x28 0x29 nd High-pass 2 order filter 0x2A for XO = 000 0x2B 0x2C 0x2D 0x2E nd Low-pass 2 order filter 0x2F for XO = 000 0x30 0x31 0x32 Channel 1 - Prescale 0x33 Channel 2 - Prescale ...

Page 52

... A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x000C specifies approximately 1 ms. 52/ MPCC13 MPCC12 MPCC5 MPCC4 FDRC13 FDRC12 0 0 FDRC5 FDRC4 0 0 Doc ID 11531 Rev MPCC11 MPCC10 MPCC9 MPCC3 MPCC2 MPCC1 FDRC11 FDRC10 FDRC9 FDRC3 FDRC2 FDRC1 STA326 D0 MPCC8 1 MPCC0 0 D0 FDRC8 0 FDRC0 0 ...

Page 53

Applications Figure 19. Application circuit for 2.1/2.0 configurable solution ...

Page 54

Package mechanical data Figure 20. PowerSO-36 EPU outline drawing ...

Page 55

... STA326 Table 64. PowerSO-36 EPU dimensions Symbol Min A 3.25 A2 3. 0.03 b 0.22 c 0.23 D 15. 13.90 E1 10. 5. 15. 0. order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...

Page 56

... Chapter 4: Characterization curves on page 13 3 Updated Table 9: Register summary on page 18 in register description Updated reset values in register bit map tables in Register description on page 18 Updated Chapter 8: Applications on page 53 Updated Chapter 9: Package mechanical data on page 54 Doc ID 11531 Rev 3 STA326 Changes with bit names used Chapter 6: ...

Page 57

... STA326 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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