STA326 STMicroelectronics, STA326 Datasheet - Page 9

• Manufacturer Part Number: STA326
• Description: DIG AUDIO SYSTEM, 2-CH, 36POWERSSOP
• Manufacturer: STMicroelectronics

Specifications of STA326

• Svhc: No SVHC (15-Dec-2010)
• No. Of Pins: 36
• Operating Temperature Range: -20°C To +85°C
• Supply Voltage Max: 36V
• Supply Voltage Min: 10V
• Termination T: RoHS Compliant
• Package / Case: PowerSO
• Interface: I2C
• Interface Type: I2C
• Rohs Compliant: Yes

STA326
2.3
Pin description
OUT1A, 1B, 2A and 2B (pins 16, 10, 9 and 3)
Output half bridge PWM outputs 1A, 1B, 2A and 2B provide the input signals to the
speakers.
RESET (pin 22)
Driving RESET low sets all outputs low and returns all register settings to their default
(reset) values. The reset is asynchronous to the internal clock.
I
The SDA (I
(Chapter 5 on page 15
supported.
GNDA and VDDA (pins 28 and 29)
This is the 3.3 V analog supply for the phase locked loop. It must be well decoupled and
filtered for good noise immunity since the audio performance of the device depends upon
the PLL circuit.
CLK (pin 27)
This is the master clock in used by the digital core. The master clock must be an integer
multiple of the LR clock frequency. Typically, the master clock frequency is 12.288 MHz
(256 * fs) for a 48 kHz sample rate; it is the default setting at power-up. Care must be taken
to provide the device with the nominal system clock frequency; over-clocking the device may
result in anomalous operation, such as inability to communicate.
FILTER_PLL (pin 26)
This is the connection for external filter components for the PLL loop compensation. The
schematic diagram in
BICKI (pin 32)
The serial or bit clock input is for framing each data bit. The bit clock frequency is typically
64 * fs using I
SDI_12 (pin 30)
This is the serial data input where PCM audio information enters the device. Six format
choices are available including I
of 16, 18, 20 and 24 bits.
LRCKI (pin 31)
The left/right clock input is for data word framing. The clock frequency is at the input sample
rate, fs.
2
C
signals (pins 23 and 24)
2
C Data) and SCL (I
2
S serial format.
Figure 19 on page 53
gives more information). Fast-mode (400 kB/s) I
Doc ID 11531 Rev 3
2
2
C Clock) pins operate according to the I
S, left or right justified, LSB or MSB first, with word widths
shows the recommended circuit.
2
C communication is
2
C specification
Pin out
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