LFE2-12E-5FN256C LATTICE SEMICONDUCTOR, LFE2-12E-5FN256C Datasheet - Page 32
LFE2-12E-5FN256C
Manufacturer Part Number
LFE2-12E-5FN256C
Description
IC, LATTICEECP2 FPGA, 420MHZ, FPBGA-256
Manufacturer
LATTICE SEMICONDUCTOR
Series
LatticeECP2r
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2-12E-5FN256C
No. Of Logic Blocks
12000
No. Of Macrocells
6000
No. Of Speed Grades
5
No. Of I/o's
193
Clock Management
DLL, PLL
I/o Supply Voltage
3.465V
Total Ram Bits
221Kbit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-12E-5FN256C
Manufacturer:
Lattice
Quantity:
135
Company:
Part Number:
LFE2-12E-5FN256C
Manufacturer:
LG
Quantity:
6 317
Company:
Part Number:
LFE2-12E-5FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 2-28. PIC Diagram
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-28.
The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right
edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs.
DDRCLKPOL*
*Signals are available on left/right/bottom edges only.
** Selected blocks.
DQSXFER*
QNEG0*
QNEG1*
ONEG2*
QPOS0*
QPOS1*
OPOS2*
ONEG0
OPOS0
ONEG1
INDD
OPOS1
INCK**
ECLK1
ECLK2
IPOS0
IPOS1
GSRN
INFF
CLK
LSR
CE
TD
Control
Muxes
CLK1
CLK0
CEO
GSR
LSR
CEI
2-29
PIOA
Register
Register
Register
Tristate
Output
Block
Block
Block
Input
PIOB
IOLD0
IOLT0
DI
LatticeECP2/M Family Data Sheet
Buffer
sysIO
PADB
PADA
“C”
“T”
Architecture
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