XC2C384-10TQG144C Xilinx Inc, XC2C384-10TQG144C Datasheet - Page 3

• Manufacturer Part Number: XC2C384-10TQG144C
• Description: IC, CPLD, 384 MACROCELL, 7.1NS, TQFP-144
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C384-10TQG144C

• No. Of Macrocells: 384
• No. Of I/o's: 118
• Propagation Delay: 7.1ns
• Global Clock Setup Time: 3.3ns
• Frequency: 125MHz
• Supply Voltage Range: 1.7V To 1.9V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 9.2ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 24
• Number Of Macrocells: 384
• Number Of Gates: 9000
• Number Of I /o: 118
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Features: JTAG
• Voltage: 1.8V
• Memory Type: CMOS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1406

the same V
CoolRunner-II CPLD I/O standards.)
Table 4: CoolRunner-II CPLD Family Features
Architecture Description
CoolRunner-II CPLD is a highly uniform family of fast, low
power CPLDs. The underlying architecture is a traditional
CPLD architecture combining macrocells into Function
Blocks (FBs) interconnected with a global routing matrix,
the Xilinx Advanced Interconnect Matrix (AIM). The FBs use
a Programmable Logic Array (PLA) configuration which
allows all product terms to be routed and shared among any
of the macrocells of the FB. Design software can efficiently
synthesize and optimize logic that is subsequently fit to the
FBs and connected with the ability to utilize a very high per-
centage of device resources. Design changes are easily
and automatically managed by the software, which exploits
the 100% routability of the Programmable Logic Array within
each FB. This extremely robust building block delivers the
DS090 (v3.1) September 11, 2008
Product Specification
1.
IEEE 1532
I/O banks
Clock division
DualEDGE
Registers
DataGATE
LVTTL
LVCMOS33, 25,
18, and 15
SSTL2_1
SSTL3_1
HSTL_1
Configurable
ground
Quadruple data
security
Open drain outputs
Hot plugging
Schmitt Inputs
LVCMOS15 requires the use of Schmitt-trigger inputs.
(1)
R
CCIO
level. (See
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industry’s highest pinout retention, under very broad design
conditions. The architecture is explained in more detail with
the discussion of the underlying FBs, logic and intercon-
nect.
The design software automatically manages these device
resources so that users can express their designs using
completely generic constructs without knowledge of these
architectural details. More advanced users can take advan-
tage of these details to more thoroughly understand the
software’s choices and direct its results.
Figure 1
attach to pins and interconnect to each other within the
internal interconnect matrix. Each FB contains 16 macro-
cells. The BSC path is the JTAG Boundary Scan Control
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shows the high-level architecture whereby FBs
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CoolRunner-II CPLD Family
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