IS42S16160B-7BL INTEGRATED SILICON SOLUTION (ISSI), IS42S16160B-7BL Datasheet

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IS42S16160B-7BL

Manufacturer Part Number
IS42S16160B-7BL
Description
IC, SDRAM, 256MBIT, 143MHZ, TSOP-54
Manufacturer
INTEGRATED SILICON SOLUTION (ISSI)
Datasheet

Specifications of IS42S16160B-7BL

Memory Type
DRAM - Sychronous
Memory Configuration
8M X 4
Access Time
7ns
Page Size
256Mbit
Ic Interface Type
Parallel
Memory Case Style
TSOP
No. Of Pins
54
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
IS42S83200B
IS42S16160B
32Meg x 8, 16Meg x16
256-MBIT SYNCHRONOUS DRAM
FEATURES
• Clock frequency: 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a
• Internal bank for hiding row access/precharge
• Power supply
• LVTTL interface
• Programmable burst length
• Programmable burst sequence:
• Auto Refresh (CBR)
• Self Refresh
• 8K refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
• Burst termination by burst stop and precharge
• Available in Industrial Temperature
• Available in 54-pin TSOP-II and 54-ball BGA
• Available in Lead-free
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
07/28/08
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
positive clock edge
IS42S83200B
IS42S16160B
– (1, 2, 4, 8, full page)
Sequential/Interleave
operations capability
command
(x16 only)
V
3.3V 3.3V
3.3V 3.3V
DD
V
DDQ
KEY TIMING PARAMETERS
OVERVIEW
ISSI
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
The 256Mb SDRAM is organized as follows.
IS42S83200B
8M x 8 x 4 Banks 4M x16x4 Banks
54-pin TSOPII
Parameter
Clk Cycle Time
Clk Frequency
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
's 256Mb Synchronous DRAM achieves high-speed
IS42S16160B
54-pin TSOPII
54-ball BGA
166
125
SEPTEMBER 2008
5.4
6.5
-6
6
8
143
100
5.4
6.5
10
-7
7
Unit
Mhz
Mhz
ns
ns
ns
ns
1

Related parts for IS42S16160B-7BL

IS42S16160B-7BL Summary of contents

Page 1

... Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows. IS42S83200B IS42S16160B Banks 4M x16x4 Banks 54-pin TSOPII 54-pin TSOPII 54-ball BGA KEY TIMING PARAMETERS ...

Page 2

... IS42S83200B, IS42S16160B DEVICE OVERVIEW The 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V V and 3.3V V memory systems containing 268,435,456 DDQ bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 67,108,864-bit bank is orga- nized as 8,192 rows by 512 columns by 16 bits or 8,192 rows by 1,024 columns by 8 bits ...

Page 3

... IS42S83200B, IS42S16160B PIN CONFIGURATIONS 54 pin TSOP - Type II for x8 PIN DESCRIPTIONS A0-A12 Row Address Input A0-A9 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ7 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command ...

Page 4

... IS42S83200B, IS42S16160B PIN CONFIGURATIONS 54 pin TSOP - Type II for x16 PIN DESCRIPTIONS A0-A12 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command ...

Page 5

... IS42S83200B, IS42S16160B PIN CONFIGURATION 54-ball fBGA for x16 (Top View) (8. 13.00 mm Body, 0.8 mm Ball Pitch) PACKAGE CODE PIN DESCRIPTIONS A0-A12 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE ...

Page 6

... DQML or DQMH is LOW, the corresponding buffer byte is enabled, and data can be written to the device. WhenDQML or DQMH is HIGH, input data is masked and cannot be written to the device. For IS42S16160B only. For IS42S83200B only. Data on the Data Bus is latched on DQ pins during Write commands, and buffered for output after Read commands. RAS, in conjunction with CAS and WE, forms the device command. See the " ...

Page 7

... IS42S83200B, IS42S16160B GENERAL DESCRIPTION READ The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0-A9 (x8); A0-A8 (x16) provides the starting column location. When A10 is HIGH, this command functions as an AUTO PRECHARGE command. When the auto precharge is selected, the row being accessed will be precharged at the end of the READ burst ...

Page 8

... IS42S83200B, IS42S16160B COMMAND TRUTH TABLE CKE Function n – 1 Device deselect (DESL operation (NOP) H Burst stop (BST) H Read H Read with auto precharge H Write H Write with auto precharge H Bank activate (ACT) H Precharge select bank (PRE) H Precharge all banks (PALL) H CBR Auto-Refresh (REF) H Self-Refresh (SELF) ...

Page 9

... IS42S83200B, IS42S16160B CKE TRUTH TABLE Current State /Function Activating Clock suspend mode entry Any Clock suspend mode Clock suspend mode exit Auto refresh command Idle (REF) Self refresh entry Idle (SELF) Power down entry Idle Self refresh exit Power down exit ...

Page 10

... IS42S83200B, IS42S16160B FUNCTIONAL TRUTH TABLE CS CS RAS RAS CAS CAS RAS RAS CAS RAS CAS CAS Current State Idle Row Active Read Write Note: H Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Address Command X X DESL H X NOP L X BST ...

Page 11

... IS42S83200B, IS42S16160B FUNCTIONAL TRUTH TABLE Continued RAS RAS CAS RAS CAS CAS CAS CS CS RAS RAS CAS Current State Read with auto H × × Precharging Write with Auto H × × Precharge Precharging H × × Row Activating H × × Note: H=V , L=V ...

Page 12

... IS42S83200B, IS42S16160B FUNCTIONAL TRUTH TABLE Continued RAS RAS RAS CAS CAS CAS CAS CS CS RAS RAS CAS Current State Write Recovering H × × Write Recovering H × × with Auto Precharge Refresh H × × Mode Register H × × Accessing × Note: H=V ...

Page 13

... IS42S83200B, IS42S16160B CKE RELATED COMMAND TRUTH TABLE Current State Operation Self-Refresh (S.R.) INVALID, CLK ( would exit S.R. Self-Refresh Recovery Self-Refresh Recovery Illegal Illegal Maintain S.R. Self-Refresh Recovery Idle After t RC Idle After t RC Illegal Illegal Begin clock suspend next cycle Begin clock suspend next cycle ...

Page 14

... IS42S83200B, IS42S16160B STATE DIAGRAM Mode Register Set BST Write CKE WRITE WRITE SUSPEND CKE CKE WRITEA WRITEA SUSPEND CKE Precharge POWER ON 14 SELF SELF exit MRS REF IDLE CKE CKE ACT CKE Row Active CKE BST Read Write Read READ Write ...

Page 15

... IS42S83200B, IS42S16160B ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage DD MAX V Maximum Supply Voltage for Output Buffer DDQ MAX V Input Voltage IN V Output Voltage OUT P Allowable Power Dissipation D MAX I Output Shorted Current CS T Operating Temperature OPR T Storage Temperature STG Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 16

... IS42S83200B, IS42S16160B DC ELECTRICAL CHARACTERISTICS 1 Symbol Parameter I Operating Current (1) DD1 I Precharge Standby Current DD2P (In Power-Down Mode) I Precharge Standby Current DD2PS (In Power-Down Mode) I Precharge Standby Current (2) DD2N (In Non Power-Down Mode) I Precharge Standby Current DD2NS (In Non Power-Down Mode) I Active Standby Current (2) DD3N (In Non Power-Down Mode) ...

Page 17

... IS42S83200B, IS42S16160B AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Cycle Time CK3 t CK2 t Access Time From CLK AC3 t AC2 t CLK HIGH Level Width CHI t CLK LOW Level Width CL t Output Data Hold Time OH3 t OH2 t Output LOW Impedance Time LZ t Output HIGH Impedance Time ...

Page 18

... IS42S83200B, IS42S16160B OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency (CAS Latency = 3) CAS Latency t CAC t Active Command To Read/Write Command Delay Time RCD RAS Latency ( RAC RCD CAC t Command Period (REF to REF / ACT to ACT Command Period (ACT to PRE) ...

Page 19

... IS42S83200B, IS42S16160B AC TEST CONDITIONS Input Load t CHI 3.0V 1.4V CLK 3.0V INPUT 1. OUTPUT 1.4V AC TEST CONDITIONS Parameter AC Input Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Measurement Reference Level Integrated Silicon Solution, Inc. — www.issi.com Rev. D 07/28/08 ...

Page 20

... IS42S83200B, IS42S16160B FUNCTIONAL DESCRIPTION The 256Mb SDRAMs are quad-bank DRAMs which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits or 8,192 rows by 1,024 columns by 8 bits. Read and write accesses to the SDRAM are burst oriented ...

Page 21

... IS42S83200B, IS42S16160B INITIALIZE AND LOAD MODE REGISTER CLK CKS CKH CKE CMH CMS CMH CMS COMMAND NOP PRECHARGE DQM/ DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 ALL BANKS Power-up: V Precharge CC and CLK stable all banks T = 200µs Min. ...

Page 22

... IS42S83200B, IS42S16160B AUTO-REFRESH CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z Notes: 1. CAS latency = Auto NOP NOP Refresh Integrated Silicon Solution, Inc. — www.issi.com ...

Page 23

... IS42S83200B, IS42S16160B SELF-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge all active banks Integrated Silicon Solution, Inc. — www.issi.com Rev. D 07/28/08 ...

Page 24

... IS42S83200B, IS42S16160B REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power ...

Page 25

... IS42S83200B, IS42S16160B BURST LENGTH Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length deter- mines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst ...

Page 26

... IS42S83200B, IS42S16160B CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge ...

Page 27

... IS42S83200B, IS42S16160B CHIP OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank) ...

Page 28

... IS42S83200B, IS42S16160B READS READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst ...

Page 29

... IS42S83200B, IS42S16160B possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until the row precharge time is hidden during the access of the last data element(s). ...

Page 30

... IS42S83200B, IS42S16160B RW1 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 2 RW2 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL NOP NOP NOP NOP n+1 D n+2 OUT OUT OUT NOP NOP NOP OUT CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com ...

Page 31

... IS42S83200B, IS42S16160B CONSECUTIVE READ BURSTS T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 07/28/ NOP NOP NOP READ BANK, COL n+1 D OUT OUT ...

Page 32

... IS42S83200B, IS42S16160B RANDOM READ ACCESSES T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - READ READ READ BANK, BANK, BANK, COL b COL m COL OUT OUT CAS Latency - READ READ READ NOP BANK, BANK, BANK, COL b ...

Page 33

... IS42S83200B, IS42S16160B READ BURST TERMINATION T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 07/28/ BURST NOP NOP NOP TERMINATE n+1 D OUT OUT T2 T3 ...

Page 34

... IS42S83200B, IS42S16160B ALTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD t - BANK 0 RAS t - BANK 0 RC Notes: 1) CAS latency = 2, Burst Length = 4 2) x16: A9, A11, and A12 = " ...

Page 35

... IS42S83200B, IS42S16160B READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11, A12 ROW COLUMN A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1) CAS latency = 2, Burst Length = Full Page 2) x16: A9, A11, and A12 = "Don't Care" ...

Page 36

... IS42S83200B, IS42S16160B READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE A10 ROW DISABLE AUTO PRECHARGE BA0, BA1 BANK DQ t RCD Notes: 1) CAS latency = 2, Burst Length = 4 2) x16: A9, A11, and A12 = "Don't Care" ...

Page 37

... IS42S83200B, IS42S16160B READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 07/28/ NOP NOP NOP PRECHARGE BANK (a or all n+1 ...

Page 38

... IS42S83200B, IS42S16160B WRITES WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE COMMAND CLK HIGH CKE CS RAS CAS WE A0-A9 COLUMN ADDRESS A11, A12 AUTO PRECHARGE A10 NO PRECHARGE BA0, BA1 BANK ADDRESS Note "Don't Care" for x16. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access ...

Page 39

... IS42S83200B, IS42S16160B WRITE BURST COMMAND ADDRESS WRITE TO WRITE RANDOM WRITE CYCLES COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com Rev. D 07/28/ CLK WRITE NOP NOP BANK, COL n CLK COMMAND WRITE NOP BANK, ADDRESS COL n DON'T CARE CLK WRITE WRITE WRITE BANK, ...

Page 40

... IS42S83200B, IS42S16160B WRITE to READ T0 CLK COMMAND WRITE BANK, ADDRESS COL WP1 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL NOP READ NOP BANK, COL b D n+1 IN CAS Latency - NOP NOP PRECHARGE BANK (a or all) t DPL D n Integrated Silicon Solution, Inc. — www.issi.com ...

Page 41

... IS42S83200B, IS42S16160B WP2 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com Rev. D 07/28/ NOP NOP PRECHARGE BANK (a or all) t DPL D n CLK BURST WRITE TERMINATE COMMAND BANK, (ADDRESS) COL n ...

Page 42

... IS42S83200B, IS42S16160B WRITE - FULL PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1) Burst Length = Full Page 2) x16: A9, A11, and A12 = "Don't Care" x8: A11 and A12 = "Don't Care" ...

Page 43

... IS42S83200B, IS42S16160B WRITE - DQM OPERATION T0 t CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW BA0, BA1 BANK DQ Notes: 1) Burst Length = 4 2) x16: A9, A11, and A12 = "Don't Care" x8: A11 and A12 = "Don't Care" ...

Page 44

... IS42S83200B, IS42S16160B ALTERNATING BANK WRITE ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/DQML DQMH A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD t - BANK 0 RAS t - BANK 0 RC Notes: 1) Burst Length = 4 2) x16: A9, A11, and A12 = " ...

Page 45

... IS42S83200B, IS42S16160B CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. ...

Page 46

... IS42S83200B, IS42S16160B CLOCK SUSPEND MODE CLK CKS CKH CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM/DQML DQMH (2) A0-A9, A11, A12 COLUMN A10 BA0, BA1 BANK DQ Notes: 1) CAS latency = 3, Burst Length = 2, Auto Precharge is disabled. 2) X16: A9, A11, and A12 = "Don't Care" ...

Page 47

... IS42S83200B, IS42S16160B PRECHARGE The PRECHARGE command (see figure) is used to deac- tivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (t ) after the PRECHARGE RP command is issued. Input A10 determines whether one or ...

Page 48

... IS42S83200B, IS42S16160B POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/DQML DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Two clock cycles Precharge all All banks idle, enter active banks power-down mode ...

Page 49

... IS42S83200B, IS42S16160B BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation ( ...

Page 50

... IS42S83200B, IS42S16160B WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing (CAS latency) later. The PRECHARGE to bank n will begin after t where t begins when the READ to bank m is registered. ...

Page 51

... IS42S83200B, IS42S16160B SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 1 2) x16: A9, A11, and A12 = "Don't Care" ...

Page 52

... IS42S83200B, IS42S16160B SINGLE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 1 2) x16: A9, A11, and A12 = " ...

Page 53

... IS42S83200B, IS42S16160B READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 4 2) x16: A9, A11, and A12 = "Don't Care" ...

Page 54

... IS42S83200B, IS42S16160B READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 4 2) x16: A9, A11, A12 = " ...

Page 55

... IS42S83200B, IS42S16160B SINGLE WRITE WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM/DQML, DQMH A0-A9, A11, A12 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 1 2) x16: A9, A11, and A12 = "Don't Care" ...

Page 56

... IS42S83200B, IS42S16160B SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW DISABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 1 2) x16: A9, A11, and A12 = "Don't Care" ...

Page 57

... IS42S83200B, IS42S16160B WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/DQML DQMH A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK RCD t RAS t RC Notes: 1) Burst Length = 4 2) x16: A9, A11, and A12 = "Don't Care" ...

Page 58

... IS42S83200B, IS42S16160B WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 4 2) x16: A9, A11, and A12 = "Don't Care" ...

Page 59

... IS42S16160B-7B ORDERING INFORMATION - V Industrial Range: - Frequency Speed (ns) Order Part No. 143 MHz 7 IS42S83200B-7TI Frequency Speed (ns) Order Part No. 143 MHz 7 IS42S16160B-7TI 143 MHz 7 IS42S16160B-7BI Integrated Silicon Solution, Inc. — www.issi.com Rev. D 07/28/08 = 3.3V DD Package 54-Pin TSOPII 54-Pin TSOPII Package 54-Pin TSOPII 54-Pin TSOPII 54-ball BGA = 3 ...

Page 60

... Frequency Speed (ns) Order Part No. 166 MHz 6 IS42S16160B-6TLI 166 MHz 6 IS42S16160B-6BLI 143 MHz 7 IS42S16160B-7TLI 143 MHz 7 IS42S16160B-7BLI 60 = 3.3V DD Package 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free Package 54-Pin TSOPII, Lead-free 54-ball fBGA, Lead-free 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free 54-ball fBGA, Lead-free = 3.3V ...

Page 61

...

Page 62

PACKAGING INFORMATION Plastic TSOP 54–Pin, 86-Pin Package Code: T (Type II Plastic TSOP (T - Type II) Millimeters Symbol Min Max Ref. Std. No. Leads ( — 1.20 — A1 0.05 0.15 A2 ...

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