IS42S16160B-7TL INTEGRATED SILICON SOLUTION (ISSI), IS42S16160B-7TL Datasheet - Page 2

• Manufacturer Part Number: IS42S16160B-7TL
• Description: IC, SDRAM, 256MBIT, 143MHZ, TSOP-54
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS42S16160B-7TL

• Memory Type: DRAM - Sychronous
• Memory Configuration: 32M X 8
• Access Time: 7ns
• Page Size: 256Mbit
• Ic Interface Type: Parallel
• Memory Case Style: TSOP
• No. Of Pins: 54
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S83200B,
DEVICE OVERVIEW
The 256Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V V
and 3.3V V
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 67,108,864-bit bank is orga-
nized as 8,192 rows by 512 columns by 16 bits or 8,192 rows
by 1,024 columns by 8 bits.
The 256Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK. All
inputs and outputs are LVTTL compatible.
The 256Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during burst
access.
FUNCTIONAL BLOCK DIAGRAM (FOR 4MX16X4 BANKS SHOWN)
2
CKE
RAS
CAS
A10
A12
CLK
BA0
BA1
A11
WE
CS
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DDQ
memory systems containing 268,435,456
GENERATOR
COMMAND
DECODER
13
CLOCK
&
ADDRESS
LATCH
ROW
IS42S16160B
9
ADDRESS BUFFER
BURST COUNTER
ADDRESS LATCH
REGISTER
MODE
COLUMN
COLUMN
13
13
CONTROLLER
REFRESH
COUNTER
REFRESH
CONTROLLER
REFRESH
ADDRESS
BUFFER
SELF
DD
ROW
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE func-
tion enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting at
a selected location and continuing for a programmed num-
ber of locations in a programmed sequence. The registra-
tion of an ACTIVE command begins accesses, followed by
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A12 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
Programmable READ or WRITE burst lengths consist of 1,
2, 4 and 8 locations or full page, with a burst terminate
option.
BANK CONTROL LOGIC
Integrated Silicon Solution, Inc. — www.issi.com
13
8192
16
16
8192
8192
8192
DATA OUT
BUFFER
BUFFER
9
DATA IN
(x 16)
COLUMN DECODER
512
SENSE AMP I/O GATE
MEMORY CELL
BANK 0
16
16
ARRAY
2
DQML
DQMH
DQ 0-15
V
V
DD
ss
/V
/V
ss
DDQ
Q
07/28/08
Rev. D