IS61LV25616AL-10TL INTEGRATED SILICON SOLUTION (ISSI), IS61LV25616AL-10TL Datasheet - Page 10

• Manufacturer Part Number: IS61LV25616AL-10TL
• Description: IC, SRAM, 4MBIT, 10NS, TSOP-2-44
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS61LV25616AL-10TL

• Memory Size: 4Mbit
• Memory Configuration: 256K X 16
• Access Time: 10ns
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TSOP-2
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10
IS61LV25616AL
AC WAVEFORMS
WRITE CYCLE NO. 3
WRITE CYCLE NO. 4
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
states to initiate a Write, but any can be deasserted to terminate the Write. The
rising or falling edge of the signal that terminates the Write.
ADDRESS
ADDRESS
UB, LB
UB, LB
D
D
OUT
OUT
WE
D
WE
OE
D
CE
OE
CE
IN
IN
LOW
LOW
LOW
DATA UNDEFINED
(WE Controlled. OE is LOW During Write Cycle)
(LB, UB Controlled, Back-to-Back Write)
t
DATA UNDEFINED
SA
t
HZWE
ADDRESS 1
t
SD
t
t
SA
WORD 1
WC
t
PBW
HIGH-Z
Integrated Silicon Solution, Inc. — www.issi.com —
DATA
VALID
t
t
AW
HZWE
IN
VALID ADDRESS
t
t
PWE2
t
WC
t
PBW
t
HD
HA
t
HIGH-Z
SA
ADDRESS 2
t
t
SD
DATA
t
SD
(1,3)
WC
WORD 2
t
PBW
IN
DATA
VALID
VALID
t
SA
(1)
IN
,
t
t
HD
HA
t
LZWE
t
,
LZWE
t
t
SD
t
HA
HD
t
, and
HA
t
HD
UB_CEWR3.eps
UB_CEWR4.eps
timing is referenced to the
ISSI
1-800-379-4774
02/14/06
Rev. E
®