IS61WV6416BLL-12TLI INTEGRATED SILICON SOLUTION (ISSI), IS61WV6416BLL-12TLI Datasheet

IC, SRAM, 1MBIT, 12NS, TSOP-32

IS61WV6416BLL-12TLI

Manufacturer Part Number
IS61WV6416BLL-12TLI
Description
IC, SRAM, 1MBIT, 12NS, TSOP-32
Manufacturer
INTEGRATED SILICON SOLUTION (ISSI)
Datasheet

Specifications of IS61WV6416BLL-12TLI

Memory Size
1Mbit
Memory Configuration
64K X 16
Access Time
12ns
Supply Voltage Range
3V To 3.6V
Memory Case Style
TSOP
No. Of Pins
32
Operating Temperature Range
-40°C To +85°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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FUNCTIONAL BLOCK DIAGRAM
IS64WV6416BLL
IS61WV6416BLL
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. C
10/10/06
FEATURES
• High-speed access time:
• CMOS low power operation:
• TTL compatible interface levels
• Fully static operation: no clock or refresh
• Three state outputs
• Data control for upper and lower bytes
• Automotive Temperature Available
• Lead-free available
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
64K x 16 HIGH-SPEED CMOS STATIC RAM
12 ns: 3.3V + 10%
15 ns: 2.5V-3.6V
50 mW (typical) operating
25 µW (typical) standby
required
Lower Byte
Upper Byte
I/O8-I/O15
I/O0-I/O7
A0-A15
V
GND
DD
WE
CE
OE
UB
LB
DECODER
CIRCUIT
CONTROL
CIRCUIT
DATA
I/O
1-800-379-4774
DESCRIPTION
The
bit static RAM organized as 65,536 words by 16 bits. It is
fabricated using
technology. This highly reliable process coupled with inno-
vative circuit design techniques, yields access times as
fast as 12ns (3.3V + 10%) and 15ns (2.5V-3.6V) with low
power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61/64WV6416BLL is packaged in the JEDEC stan-
dard 44-pin TSOP-II, 44-pin 400-mil SOJ, and 48-pin mini
BGA (6mm x 8mm).
MEMORY ARRAY
ISSI
COLUMN I/O
64K x 16
IS61/64WV6416BLL is a high-speed, 1,048,576-
ISSI
's high-performance CMOS
OCTOBER 2006
ISSI
®
1

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IS61WV6416BLL-12TLI Summary of contents

Page 1

... IS64WV6416BLL IS61WV6416BLL 64K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES • High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V • CMOS low power operation (typical) operating 25 µW (typical) standby • TTL compatible interface levels • Fully static operation: no clock or refresh required • Three state outputs • ...

Page 2

... IS64WV6416BLL IS61WV6416BLL PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm I I GND I/O A14 I/O A15 I/O A12 NC A13 A10 A9 PIN DESCRIPTIONS A0-A15 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) ...

Page 3

... IS61WV6416BLL TRUTH TABLE Mode Not Selected X Output Disabled H X Read Write ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND TERM T Storage Temperature STG P Power Dissipation Related to GND DD DD Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 4

... IS64WV6416BLL IS61WV6416BLL DC ELECTRICAL CHARACTERISTICS V = 2.5V-3.6V DD Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH (1) V Input LOW Voltage IL I Input Leakage LI I Output Leakage LO Note (min.) = –0.3V DC; V (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested (max 0.3V DC ...

Page 5

... IS61WV6416BLL POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions I V Dynamic Operating Supply Current I OUT I Operating Supply Current Iout = 0mA CMOS Standby ≥ V Current (CMOS Inputs) ≥ ≤ 0.2V Note address and data inputs are cycling at the maximum frequency means no input lines change. ...

Page 6

... IS64WV6416BLL IS61WV6416BLL AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (V ) Ref Output Load AC TEST LOADS Zo=50Ω OUTPUT Figure 1a. 6 Unit (2.5V-3.6V) (3. 1.5ns See Figures 1a and 1b See Figures 1a and 1b 50Ω ...

Page 7

... IS61WV6416BLL READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time OHA CE Access Time t ACE OE Access Time t DOE OE to High-Z Output t (2) HZOE OE to Low-Z Output t (2) LZOE CE to High-Z Output t (2 HZCE CE to Low-Z Output ...

Page 8

... IS64WV6416BLL IS61WV6416BLL AC WAVEFORMS (Address Controlled) ( (1,2) READ CYCLE NO. 1 ADDRESS D OUT PREVIOUS DATA VALID (1,3) READ CYCLE NO. 2 ADDRESS LZCE LB LZB HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB Address is valid prior to or coincident with CE LOW transition. ...

Page 9

... WE HIGH to Low-Z Output t (3) LZWE Notes: 1. Test conditions for IS61WV6416BLL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels and output loading specified in Figure 1a Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. ...

Page 10

... IS64WV6416BLL IS61WV6416BLL (CE Controlled HIGH or LOW) WRITE CYCLE NO. 1 (1,2) ADDRESS UB DATA UNDEFINED OUT VALID ADDRESS t SCE PWE1 t PWE2 t PBW t HZWE HIGH DATA VALID IN Integrated Silicon Solution, Inc. — www.issi.com — ISSI ® LZWE t HD UB_CEWR1.eps 1-800-379-4774 Rev. C 10/10/06 ...

Page 11

... IS61WV6416BLL (1) (WE Controlled HIGH during Write Cycle) WRITE CYCLE NO. 2 ADDRESS OE CE LOW UB DATA UNDEFINED OUT D IN (WE Controlled LOW During Write Cycle) WRITE CYCLE NO. 3 ADDRESS OE LOW CE LOW UB DATA UNDEFINED OUT D IN Integrated Silicon Solution, Inc. — www.issi.com — Rev. C 10/10/06 ...

Page 12

... IS64WV6416BLL IS61WV6416BLL (LB, UB Controlled, Back-to-Back Write) WRITE CYCLE NO. 4 ADDRESS OE CE LOW WE UB HZWE D OUT DATA UNDEFINED D IN Notes: 1. The internal Write time is defined by the overlap LOW, UB and/ LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The referenced to the rising or falling edge of the signal that terminates the Write ...

Page 13

... IS61WV6416BLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter V V for Data Retention Data Retention Current DR t Data Retention Setup Time SDR t Recovery Time RDR Note: 1. Typical values are measured 2.5V DATA RETENTION WAVEFORM V DD 1.65V 1. GND Integrated Silicon Solution, Inc. — www.issi.com — ...

Page 14

... IS61WV6416BLL ORDERING INFORMATION Commercial Temperature Range: 0°C to +70°C Speed (ns) Order Part No. 12 IS61WV6416BLL-12KL Industrial Temperature Range: –40°C to +85°C Speed (ns) Order Part No. 12 IS61WV6416BLL-12TI 12 IS61WV6416BLL-12TLI 12 IS61WV6416BLL-12KLI 12 IS61WV6416BLL-12BI 12 IS61WV6416BLL-12BLI Temperature Range (A3): –40°C to +125°C Speed (ns) Order Part No (12 ) IS64WV6416BLL-15TA3 ...

Page 15

PACKAGING INFORMATION 400-mil Plastic SOJ Package Code Millimeters Inches Symbol Min Max Min No. Leads ( 3.25 3.75 0.128 0.148 A1 0.64 — 0.025 A2 2.08 — 0.082 B 0.38 0.51 0.015 0.020 ...

Page 16

PACKAGING INFORMATION Millimeters Inches Symbol Min Max Min No. Leads ( 3.25 3.75 0.128 0.148 A1 0.64 — 0.025 A2 2.08 — 0.082 B 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 C 0.18 0.33 0.007 0.013 ...

Page 17

PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (48-pin) Top View SEATING PLANE mBGA - 6mm x 8mm MILLIMETERS Sym. Min. Typ. Max. Min. Typ. ...

Page 18

PACKAGING INFORMATION Plastic TSOP Package Code: T (Type II Millimeters Inches Symbol Min Max Min Ref. Std. No. Leads ( — 1.20 — A1 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 ...

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