PIC16F1826-I/SO Microchip Technology, PIC16F1826-I/SO Datasheet - Page 115
PIC16F1826-I/SO
Manufacturer Part Number
PIC16F1826-I/SO
Description
IC, 8BIT MCU, PIC16F, 32MHZ, SOIC-18
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16F1826-IP.pdf
(406 pages)
3.PIC16F1826-IP.pdf
(12 pages)
4.PIC16F1826-IP.pdf
(8 pages)
5.PIC16F1826-IP.pdf
(40 pages)
6.PIC16LF1827-ISS.pdf
(400 pages)
Specifications of PIC16F1826-I/SO
Controller Family/series
PIC16F
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
32MHz
No. Of Timers
3
Interface
EUSART, I2C, SPI
Core Size
8 Bit
Program Memory Size
2kWords
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
15
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- PIC16F722-ISS PDF datasheet
- PIC16F1826-IP PDF datasheet #2
- PIC16F1826-IP PDF datasheet #3
- PIC16F1826-IP PDF datasheet #4
- PIC16F1826-IP PDF datasheet #5
- PIC16LF1827-ISS PDF datasheet #6
- Current page: 115 of 400
- Download datasheet (7Mb)
11.4
Instead of accessing program memory or EEPROM
data memory, the User ID’s, Device ID/Revision ID and
Configuration
CFGS = 1. This is the region that would be pointed to
by PC<15> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table 11-1.
TABLE 11-1:
EXAMPLE 11-3:
© 2009 Microchip Technology Inc.
* This code block will read 1 word of program
* memory at the memory address:
*
*
PROG_ADDR_HI: PROG_ADDR_LO
data will be returned in the variables;
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWL
BCF
BSF
BCF
BSF
NOP
NOP
BSF
MOVF
MOVWF
MOVF
MOVWF
Configuration Word and Device ID
Access
8000h-8003h
8007h-8008h
Address
8006h
EEADRL
PROG_ADDR_LO
EEADRL
PROG_ADDR_HI
EEADRH
EECON1,CFGS
EECON1,EEPGD
INTCON,GIE
EECON1,RD
INTCON,GIE
EEDATL,W
PROG_DATA_LO
EEDATH,W
PROG_DATA_HI
Words
PFM AND FUSE ACCESS VIA EECON1/EEDATH:EEDATL REGISTERS
(WHEN CFGS = 1)
CONFIGURATION WORD AND DEVICE ID ACCESS
can
be
Configuration Words 1 and 2
Device ID/Revision ID
accessed
; Select Bank 2
;
; Store LSB of address
;
; Store MSB of address
; Deselect Configuration Space
; Select Program Memory
; Disable interrupts
; Initiate read
; Executed (Figure 11-1)
; Ignored (Figure 11-1)
; Restore interrupts
; Get LSB of word
; Store in user location
; Get MSB of word
; Store in user location
Function
User IDs
when
Preliminary
When read access is initiated on an unallowed
address, the EEDATH:EEDATL registers are cleared.
Writes can be disabled via the WRT Configuration bits.
Refer to the Configuration Word 2.
Read Access
PIC16F/LF1826/27
Yes
Yes
Yes
Write Access
DS41391B-page 115
Yes
No
No
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