PIC16F1827-I/MQ Microchip Technology, PIC16F1827-I/MQ Datasheet
PIC16F1827-I/MQ
Specifications of PIC16F1827-I/MQ
Related parts for PIC16F1827-I/MQ
PIC16F1827-I/MQ Summary of contents
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... Flash Microcontrollers © 2009 Microchip Technology Inc. PIC16F/LF1826/27 with nanoWatt XLP Technology Preliminary Data Sheet DS41391B ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... In-Circuit Serial Programming™ (ICSP™) via two pins • In-Circuit Debug (ICD) via two pins • Enhance Low-Voltage Programming • Power-Saving Sleep mode © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Extreme Low-Power Management PIC16LF1826/27 with nanoWatt XLP: • Sleep mode • ...
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... PIC16F/LF1826/27 PIC16F/LF1826/27 Family Types Program Data Memory Memory PIC16LF1826 2K 256 PIC16F1826 2K 256 PIC16LF1827 4K 384 PIC16F1827 4K 384 One pin is input only. Note 1: DS41391B-page 4 256 2/1 256 2/1 256 4/1 256 4/1 Preliminary — — Yes — — Yes Yes Yes © 2009 Microchip Technology Inc. ...
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... PIC16F/LF1826/27 © 2009 Microchip Technology Inc. PIC16F/LF1826/27 PIC16F/LF1826/27 Preliminary DS41391B-page 5 ...
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... Note 1: ECCP2, CCP3, CCP4, MSSP2 functions are only available on the PIC16F/LF1827. 2: DS41391B-page 6 PIC16F/LF1826/27 RA7/OSC1/CLKIN/P1C 2 20 RA6/OSC2/CLKOUT/CLKR/P1D PIC16F/LF1826/ RB7/AN6/CPS6/T1OSO/P1D 7 15 RB6/AN5/CPS5/T1CKI/T1OSI/P1C Preliminary (1) (1,2) (1,2) /CCP2 /P2A (1) (1,2) (1) /P2B /SDO1 (1) (1,2) /P2B /MDCIN1/ICSPDAT (1) (1,2) (1,2) /CCP2 /P2A /ICSPCLK © 2009 Microchip Technology Inc. ...
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... Basic Pull-up Modulator Interrupt MSSP EUSART CCP Timers SR Latch Comparator Cap Sense Reference A/D ANSEL 28-Pin QFN/UQFN 20-Pin SSOP 18-Pin PDIP/SOIC I/O © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Preliminary DS41391B-page 7 ...
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... Packaging Information.............................................................................................................................................................. 377 Appendix A: Revision History............................................................................................................................................................. 387 Appendix B: Device Differences......................................................................................................................................................... 387 Index .................................................................................................................................................................................................. 389 The Microchip Web Site ..................................................................................................................................................................... 397 Customer Change Notification Service .............................................................................................................................................. 397 Customer Support .............................................................................................................................................................................. 397 Reader Response .............................................................................................................................................................................. 398 Product Identification System............................................................................................................................................................. 399 DS41391B-page 8 ) ................................................................................................................................ 321 ™ Preliminary © 2009 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Preliminary DS41391B-page 9 ...
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... PIC16F/LF1826/27 NOTES: DS41391B-page 10 Preliminary © 2009 Microchip Technology Inc. ...
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... Capture/Compare/PWM Modules ECCP1 ECCP2 CCP3 CCP4 Comparators C1 C2 Master Synchronous Serial Ports MSSP1 MSSP2 Timers Timer0 Timer1 Timer2 Timer4 Timer6 © 2009 Microchip Technology Inc. PIC16F/LF1826/27 of the ● ● ● ● ● ● ● ● ● ● ● ● ● ● ...
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... See applicable chapters for more information on peripherals. Note 1: See Table 1-1 for peripherals available on specific devices. 2: DS41391B-page 12 Program Flash Memory RAM CPU (Figure 2-1) Timer2- Timer1 DAC Comparators Types Modulator FVR EUSART CapSense Preliminary EEPROM PORTA PORTB © 2009 Microchip Technology Inc. ...
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... TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be moved using the APFCON register(s). 2: Functions are only available on the PIC16F/LF1827. 3: Default function location. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Input Output Type Type TTL CMOS General purpose I/O. ...
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... CMOS USART synchronous data C™ C™ data input/output 2. ST — SPI data input 2. — CMOS SPI data output 1. = Schmitt Trigger input with CMOS levels I Preliminary Description . OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels © 2009 Microchip Technology Inc. ...
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... TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be moved using the APFCON register(s). 2: Functions are only available on the PIC16F/LF1827. 3: Default function location. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Input Output Type Type TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. ...
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... Functions are only available on the PIC16F/LF1827. 3: Default function location. DS41391B-page 16 Input Output Type Type Power — Positive supply. Power — Ground reference. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels © 2009 Microchip Technology Inc. ...
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... Section 3.5 “Indirect Addressing”for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 28.0 “Instruction Set Summary” for more details. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Preliminary DS41391B-page 17 ...
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... Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W Reg. W reg W reg Timer Brown-out Reset Preliminary RAM Addr 9 Indirect Addr 12 FSR0 Reg. FSR reg FSR reg STATUS Reg. STATUS reg STATUS reg MUX MUX MUX © 2009 Microchip Technology Inc. ...
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... Section 11.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC16F/LF1826 PIC16F/LF1827 © 2009 Microchip Technology Inc. PIC16F/LF1826/27 The following features are associated with access and control of program memory and data memory: memory in • PCL and PCLATH • ...
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... Memory 7FFFh Preliminary PROGRAM MEMORY MAP AND STACK FOR PIC16F/LF1827 PC<14:0> 15 Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh 1000h Rollover to Page 0 Rollover to Page 1 7FFFh © 2009 Microchip Technology Inc. ...
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... The BRW instruction makes this type of table very sim- ple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Preliminary DS41391B-page 21 ...
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... STATUS • FSR0 Low • FSR0 High • FSR1 Low • FSR1 High • BSR • WREG • PCLATH • INTCON The core registers are the first 12 Note: addresses of every data memory bank. “Indirect Preliminary © 2009 Microchip Technology Inc. ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the Note 1: second operand. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘ ...
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... DS41391B-page 24 3.2.5 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: MEMORY MAP TABLES Device PIC16F/LF1826/27 Preliminary © 2009 Microchip Technology Inc. Banks Table No. 0-7 Table 3-3 8-15 Table 3-4 16-23 Table 3-5 24-31 ...
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... Microchip Technology Inc. PIC16F/LF1826/27 Preliminary DS41391B-page 25 ...
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... PIC16F/LF1826/27 DS41391B-page 26 Preliminary © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC16F/LF1826/27 Preliminary DS41391B-page 27 ...
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... PIC16F/LF1826/27 DS41391B-page 28 Preliminary © 2009 Microchip Technology Inc. ...
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... FECh FEDh STKPTR FEEh TOSL FEFh TOSH = Unimplemented data memory locations, Legend: read as ‘0’. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register Summary for the device family are as follows: Device PIC16F/LF1826/27 Preliminary Bank(s) Page No ...
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... TMR1ON 0000 00-0 uuuu uu-u T1GSS1 T1GSS0 0000 0x00 uuuu uxuu 0000 0000 0000 0000 1111 1111 1111 1111 T2CKPS1 T2CKPS0 -000 0000 -000 0000 — — T0XCS 0--- 0000 0--- 0000 CPSCH1 CPSCH0 ---- 0000 ---- 0000 © 2009 Microchip Technology Inc. ...
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... ADCS2 09Fh — Unimplemented x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. PIC16F/LF1827 only. Note 1: These registers can be addressed from any bank. 2: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... DACNSS 000- 00-0 000- 00-0 DACR1 DACR0 ---0 0000 ---0 0000 SRPS SRPR 0000 0000 0000 0000 SRRC2E SRRC1E 0000 0000 0000 0000 — — P1CSEL CCP1SEL 0000 0000 0000 0000 --- TXCKSEL ---- ---0 ---- ---0 — — © 2009 Microchip Technology Inc. ...
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... BAUDCON ABDOVF RCIDL x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. PIC16F/LF1827 only. Note 1: These registers can be addressed from any bank. 2: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... ADD1 ADD0 0000 0000 0000 0000 MSK1 MSK0 1111 1111 1111 1111 UA BF 0000 0000 0000 0000 SSPM1 SSPM0 0000 0000 0000 0000 RSEN SEN 0000 0000 0000 0000 AHEN DHEN 0000 0000 0000 0000 © 2009 Microchip Technology Inc. ...
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... C4TSEL0 29Fh — Unimplemented x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. PIC16F/LF1827 only. Note 1: These registers can be addressed from any bank. 2: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... CCP3M1 CCP3M0 --00 0000 --00 0000 — — — — — — — — xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP4M1 CCP4M0 --00 0000 --00 0000 — — — — — — — — — — © 2009 Microchip Technology Inc. ...
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... MDCARH MDCHODIS MDCHPOL MDCHSYNC x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. PIC16F/LF1827 only. Note 1: These registers can be addressed from any bank. 2: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... T4CKPS1 T4CKPS0 -000 0000 -000 0000 — — — — — — — — 0000 0000 0000 0000 1111 1111 1111 1111 T6CKPS1 T6CKPS0 -000 0000 -000 0000 — — © 2009 Microchip Technology Inc. ...
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... Legend: Shaded locations are unimplemented, read as ‘0’. PIC16F/LF1827 only. Note 1: These registers can be addressed from any bank. 2: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... Microchip Technology Inc. ...
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... GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, “Implementing a Table Read” (DS00556). © 2009 Microchip Technology Inc. PIC16F/LF1826/27 3.3.3 COMPUTED FUNCTION CALLS A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables ...
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... TOSH/TOSL registers will return ‘ ’. If the Stack Overflow/Underflow Reset is 0x05 disabled, the TOSH/TOSL registers will 0x04 return the contents of stack address 0x0F. 0x03 0x02 0x01 0x00 STKPTR = 0x1F 0x1F 0x0000 Preliminary Stack Reset Disabled (STVREN = ) Stack Reset Enabled (STVREN = ) © 2009 Microchip Technology Inc. ...
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... FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 TOSH:TOSL FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3 TOSH:TOSL © 2009 Microchip Technology Inc. PIC16F/LF1826/27 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A This figure shows the stack configuration 0x09 after the first If a 0x08 return address will be placed in the ...
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... Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will Return Address 0x06 not be overwritten. Return Address 0x05 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address STKPTR = 0x10 Return Address 0x00 Preliminary or © 2009 Microchip Technology Inc. ...
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... FIGURE 3-9: INDIRECT ADDRESSING FSR Address Range Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory ...
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... FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 0x00 0x7F DS41391B-page FSRxH Bank Select 0000 0001 0010 1111 Bank 0 Bank 1 Bank 2 Bank 31 Preliminary Indirect Addressing 0 7 FSRxL 0 Location Select © 2009 Microchip Technology Inc. ...
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... FSRnL Location Select 0x2000 0x29AF © 2009 Microchip Technology Inc. PIC16F/LF1826/27 3.5.3 PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF ...
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... PIC16F/LF1826/27 NOTES: DS41391B-page 48 Preliminary © 2009 Microchip Technology Inc. ...
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... Configuration Word 2, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Preliminary DS41391B-page 49 ...
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... BOREN1 BOREN0 R/P-1/1 R/P-1/1 R/P-1/1 WDTE1 WDTE0 FOSC2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) (2) (3) Pin Function Select bit (1) Preliminary R/P-1/1 R/P-1/1 CPD CP bit 7 R/P-1/1 R/P-1/1 FOSC1 FOSC0 bit 0 © 2009 Microchip Technology Inc. ...
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... Enabling Brown-out Reset does not automatically enable Power-up Timer. Note 1: The entire data EEPROM will be erased when the code protection is turned off during an erase. 2: The entire program memory will be erased when the code protection is turned off. 3: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Preliminary DS41391B-page 51 ...
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... DS41391B-page 52 U-1 R/P-1/1 R/P-1/1 — BORV STVREN R/P-1/1 U-1 U-1 — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/P-1/1 U-1 PLLEN — bit 7 R/P-1/1 R/P-1/1 WRT1 WRT0 bit 0 © 2009 Microchip Technology Inc. ...
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... See Section 11.4 “Configuration Word and Device ID Access” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16F/LF1826/27 Memory Programming Specification” (DS41390). © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Preliminary DS41391B-page 53 ...
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... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 13-5 DEV<8:0>: Device ID bits 100111100 = PIC16F1826 100111101 = PIC16F1827 101000100 = PIC16LF1826 101000101 = PIC16LF1827 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. This location cannot be written. Note 1: ...
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... MHz (HFINTOSC) 500 kHz 500 kHz Source (MFINTOSC) 31 kHz Source 31 kHz (LFINTOSC) © 2009 Microchip Technology Inc. PIC16F/LF1826/27 The oscillator module can be configured in one of six clock modes – External clock – 32 kHz Low-Power Crystal mode – Medium Gain Crystal or Ceramic Resonator Oscillator mode ...
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... Figure 5-3 and Figure 5-4 show typical circuits for quartz crystal and ceramic resonators, respectively. Preliminary ® MCU design is fully EXTERNAL CLOCK (EC) MODE OPERATION OSC1/CLKIN ® PIC MCU OSC2/CLKOUT/CLKR (1) I/O © 2009 Microchip Technology Inc. ...
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... AN849, “Basic PIC Oscillator Design” (DS00849) ® • AN943, “Practical PIC Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) © 2009 Microchip Technology Inc. PIC16F/LF1826/27 FIGURE 5- Internal Logic Sleep C2 Ceramic Resonator Note 1: A series resistor (R ceramic resonators with low drive level ...
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... Oscillator) is factory calibrated and operates at 500 kHz. The frequency of the MFINTOSC can be user-adjusted OSCTUNE register (Register 5-3). 3. The LFINTOSC Oscillator) is uncalibrated and operates at 31 kHz. ) values EXT Preliminary (High-Frequency Internal the HFINTOSC can be via software using the (Low-Frequency Internal © 2009 Microchip Technology Inc. ...
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... Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ The Medium Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running and can be utilized. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 5.2.2.3 Internal Oscillator Frequency Adjustment The 500 kHz internal oscillator is factory calibrated ...
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... Clock switching time delays are shown in Table 5-1. Start-up delay specifications are located in the oscillator tables of Specifications”. Preliminary © 2009 Microchip Technology Inc. the PLLEN bit in Section 29.0 “Electrical ...
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... LFINTOSC ≠ IRCF <3:0> System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Start-up Time 2-cycle Sync = 0 2-cycle Sync = 0 0 LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync ≠ 0 Preliminary ...
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... The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator. Preliminary © 2009 Microchip Technology Inc. ...
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... Any clock source LFINTOSC Any clock source Timer1 Oscillator PLL inactive PLL active PLL inactive. Note 1: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: • IESO (of the Configuration Word Inter- nal/External Switchover bit (Two-Speed Start-up mode enabled). • ...
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... CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator Preliminary © 2009 Microchip Technology Inc. ...
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... The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register ...
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... Clock Monitor Output (Q) OSCFIF The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in Note: this example have been chosen for clarity. DS41391B-page 66 Oscillator Failure Test Test Preliminary Failure Detected Test © 2009 Microchip Technology Inc. ...
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... SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1 Duplicate frequency derived from HFINTOSC. Note 1: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 R/W-1/1 R/W-1/1 IRCF1 IRCF0 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS41391B-page 68 R-0/q R-0/q R-q/q HFIOFR HFIOFL MFIOFR U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Conditional Preliminary R-0/0 R-0/q LFIOFR HFIOFS bit 0 © 2009 Microchip Technology Inc. ...
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... CONFIG1 7:0 CP MCLRE — = unimplemented locations read as ‘0’. Shaded cells are not used by clock sources. Legend: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 R/W-0/0 R/W-0/0 R/W-0/0 TUN4 TUN3 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... PIC16F/LF1826/27 NOTES: DS41391B-page 70 Preliminary © 2009 Microchip Technology Inc. ...
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... Upon any device Reset, the reference clock module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 6.3 Conflicts with the CLKR pin ...
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... To route CLKR to pin, CLKOUTEN of Configuration Word required. CLKOUTEN of Configuration Word will result in F OSC DS41391B-page 72 R/W-1/1 R/W-0/0 R/W-0/0 CLKRDC1 CLKRDC0 CLKRDIV2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (3) (1) (2) /4. Preliminary R/W-0/0 R/W-0/0 CLKRDIV1 CLKRDIV0 bit 0 © 2009 Microchip Technology Inc. ...
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... Bit -/7 Bit -/6 13:8 — — CONFIG1 7:0 CP MCLRE — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. Legend: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 CLKRDC0 CLKRDIV2 Bit 13/5 Bit 12/4 Bit 11/3 ...
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... PIC16F/LF1826/27 NOTES: DS41391B-page 74 Preliminary © 2009 Microchip Technology Inc. ...
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... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable © 2009 Microchip Technology Inc. PIC16F/LF1826/27 PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41391B-page 75 ...
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... BOR protection is unchanged by Sleep. DD Preliminary DD falls below V for a DD BOR , the device BORDC Device Device Operation upon Operation upon wake- up from release of POR Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD © 2009 Microchip Technology Inc. ...
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... If BOREN<1:0> in Configuration Word BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive © 2009 Microchip Technology Inc. PIC16F/LF1826/27 T BORRDY BOR Protection Active (1) T PWRT < T ...
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... Upon bringing MCLR high, the device will begin execution immediately (see Figure 7- 4). This is useful for testing purposes or to synchronize more than one device operating in parallel. Preliminary to stabilize before allowing the DD Timer configuration. See © 2009 Microchip Technology Inc. ...
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... FIGURE 7-4: RESET START-UP SEQUENCE V DD Internal POR Power-up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC © 2009 Microchip Technology Inc. PIC16F/LF1826/27 T PWRT T MCLR T OST Preliminary DS41391B-page 79 ...
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... Program Counter 0000h ---1 1000 0000h ---u uuuu 0000h ---1 0uuu 0000h ---0 uuuu ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition STATUS PCON Register Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu © 2009 Microchip Technology Inc. ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) © 2009 Microchip Technology Inc. PIC16F/LF1826/27 U-0 R/W/HC-1/q R/W/HC-1/q — ...
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... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. Note 1: DS41391B-page 82 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — — RMCLR RI — Preliminary Register Bit 1 Bit 0 on Page — BORRDY 77 POR BOR 103 © 2009 Microchip Technology Inc. ...
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... A block diagram of the interrupt logic is shown in Figure 8-1 and Figure 8-2. FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE From Peripheral Interrupt Logic (Figure 8-2) © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE PEIE GIE ...
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... OSFIE C2IF C2IE C1IF C1IE EEIF EEIE BCL1IF BCL1IE (1) CCP2IF (1) CCP2IE (1) CCP4IF (1) CCP4IE (1) CCP3IF (1) CCP3IE (1) TMR6IF (1) TMR6IE (1) TMR4IF (1) TMR4IE (1) BCL2IF (1) BCL2IE (1) SSP2IF (1) SSP2IE Note 1: These interrupts are available on PIC16F/LF1827 only DS41391B-page 84 Preliminary © 2009 Microchip Technology Inc. To Interrupt Logic (Figure 5-1) ...
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... All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 8.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins ...
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... Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP Preliminary 0005h Inst(0004h) 0005h Inst(0004h) 0004h 0005h NOP Inst(0004h) Inst(0005h) 0004h 0005h NOP NOP Inst(0004h) © 2009 Microchip Technology Inc. ...
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... Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 29.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. © 2009 Microchip Technology Inc. PIC16F/LF1826/ ...
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... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved. DS41391B-page 88 Preliminary © 2009 Microchip Technology Inc. ...
Page 89
... The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register ...
Page 90
... Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 R/W-0/0 TXIE SSP1IE CCP1IE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 TMR2IE TMR1IE bit 0 © 2009 Microchip Technology Inc. ...
Page 91
... Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt PIC16F/LF1827 only. Note 1: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 ...
Page 92
... Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 U-0 CCP3IE TMR6IE — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary (1) R/W-0/0 U-0 TMR4IE — bit 0 © 2009 Microchip Technology Inc. ...
Page 93
... SSP2IE: Master Synchronous Serial Port 2 (MSSP2) Interrupt Enable bit 1 = Enables the MSSP2 interrupt 0 = Disables the MSSP2 interrupt This register is only available on PIC16F/LF1827. Note 1: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Note 1: The PIE4 register is available only on the PIC16F/LF1827 device. 2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt ...
Page 94
... R-0/0 R/W-0/0 R/W-0/0 TXIF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary © 2009 Microchip Technology Inc. should ensure the R/W-0/0 R/W-0/0 TMR2IF TMR1IF bit 0 ...
Page 95
... CCP2IF: CCP2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending PIC16F/LF1827 only. Note 1: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. ...
Page 96
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. R/W-0/0 R/W-0/0 U-0 CCP3IF TMR6IF — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary (1) R/W-0/0 U-0 TMR4IF — bit 0 © 2009 Microchip Technology Inc. ...
Page 97
... Shaded cells are not used by Interrupts. Legend: PIC16F/LF1827 only. Note 1: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Note 1: The PIR4 register is available only on the PIC16F/LF1827 device. 2: Interrupt flag bits are set when an inter- rupt condition occurs, regardless of the ...
Page 98
... PIC16F/LF1826/27 NOTES: DS41391B-page 98 Preliminary © 2009 Microchip Technology Inc. ...
Page 99
... See Section 16.0 “Digital-to-Analog Con- verter (DAC) Module” and Section 14.0 “Fixed Volt- age Reference (FVR)” for more information on these modules. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1 ...
Page 100
... Inst(0005h) Dummy Cycle Inst(0004h) Register on Bit 1 Bit 0 Page INTF IOCIF 89 IOCBF1 IOCBF0 132 IOCBN1 IOCBN0 132 IOCBP1 IOCBP0 132 TMR2IE TMR1IE 90 (1) — CCP2IE 91 BCL2IE SSP2IE 93 TMR2IF TMR1IF 94 (1) — CCP2IF 95 BCL2IF SSP2IF WDTPS0 SWDTEN 103 © 2009 Microchip Technology Inc. ...
Page 101
... Configurable time-out period is from 268 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep © 2009 Microchip Technology Inc. PIC16F/LF1826/27 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41391B-page 101 ...
Page 102
... STATUS register are changed to indicate the Active event. See Section 3.0 “Memory Organization” and Active The STATUS register information. Disabled Active Disabled Disabled Preliminary (Register 3-1) for more WDT Cleared Cleared until the end of OST Unaffected © 2009 Microchip Technology Inc. ...
Page 103
... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS3 WDTPS2 WDTPS1 U = Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ...
Page 104
... PIC16F/LF1826/27 NOTES: DS41391B-page 104 Preliminary © 2009 Microchip Technology Inc. ...
Page 105
... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 11.1 EEADRL and EEADRH Registers The EEADRL and EEADRH registers can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...
Page 106
... EEADRH3 EEADRH2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u EEDATL1 EEDATL0 bit 0 R/W-x/u R/W-x/u EEDATH1 EEDATH0 bit 0 R/W-0/0 R/W-0/0 EEADR1 EEADR0 bit 0 R/W-0/0 R/W-0/0 EEADRH1 EEADRH0 bit 0 © 2009 Microchip Technology Inc. ...
Page 107
... RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 R/W/HC-0/0 R/W-x/q R/W-0/0 ...
Page 108
... Refer to Section 11.1.3 “Writing to the Data EEPROM Memory” for more information. DS41391B-page 108 R-0/0 R-0/0 R-0/0 EEPROM control register Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R-0/0 R-0/0 bit 0 © 2009 Microchip Technology Inc. ...
Page 109
... BTFSC EECON1, WR ;Wait for write to complete GOTO $-2 ;Done © 2009 Microchip Technology Inc. PIC16F/LF1826/27 11.1.3 WRITING TO THE DATA EEPROM MEMORY To write an EEPROM data location, the user must first write the address to the EEADRL register and the data to the EEDATL register. Then the user must follow a specific sequence to initiate the write for each byte ...
Page 110
... Byte of Program Address to read ; ;Point to PROGRAM memory ;EE Read ;First instruction after BSF EECON1,RD executes normally ;Any instructions here are ignored as program ;memory is read in second cycle after BSF EECON1, Byte of Program Memory ; ; Byte of Program EEDATL ; Preliminary instruction on the next © 2009 Microchip Technology Inc. ...
Page 111
... FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) BSF EECON1,RD INSTR( executed here executed here RD bit EEDATH EEDATL Register EERHLT © 2009 Microchip Technology Inc. PIC16F/LF1826/27 EEADRH,EEADRL PC+3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here Preliminary INSTR ( ...
Page 112
... Example 11-5. The initial address is loaded into the EEADRH and EEADRL register pair; the eight words of data are loaded using indirect addressing. The code sequence provided in Example Note: 12-5 must be repeated 4 times to fully program an erased program memory row of 32 words. Preliminary © 2009 Microchip Technology Inc. ...
Page 113
... FIGURE 11-2: BLOCK WRITES TO 8K FLASH PROGRAM MEMORY First word of block to be written 14 EEADRL<2:0> = 000 EEADRL<2:0> = 001 Buffer Register © 2009 Microchip Technology Inc. PIC16F/LF1826/ EEDATH EEDATA 6 14 EEADRL<2:0> = 010 Buffer Register Buffer Register Program Memory Preliminary EEADRL<2:0> = 111 Buffer Register ...
Page 114
... Write AAh ; Set WR bit to begin write ; Any instructions here are ignored as processor ; halts to begin write sequence ; Processor will stop here and wait for write complete. ; after write processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary © 2009 Microchip Technology Inc. ...
Page 115
... MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location © 2009 Microchip Technology Inc. PIC16F/LF1826/27 When read access is initiated on an unallowed address, the EEDATH:EEDATL registers are cleared. Writes can be disabled via the WRT Configuration bits. Refer to the Configuration Word 2. when ...
Page 116
... EEPROM. Bit 4 Bit 3 Bit 2 Bit 1 FREE WRERR WREN WR INTE IOCIE TMR0IF INTF EEIE BCL1IE — — EEIF BCL1IF — — Preliminary duration) prevents Register Bit 0 on Page RD 107 108* 106 106 106 106 IOCIF 89 CCP2IE 91 CCP2IF 95 © 2009 Microchip Technology Inc. ...
Page 117
... Write PORTx CK Data Register Data Bus Read PORTx To peripherals ANSELx © 2009 Microchip Technology Inc. PIC16F/LF1826/27 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCONx) registers are used to steer specific peripheral input and output functions between different pins. The APFCONx ...
Page 118
... Value at POR and BOR/Value at all other Resets U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 P1CSEL CCP1SEL bit 0 U-0 R/W-0/0 — TXCKSEL bit 0 © 2009 Microchip Technology Inc. ...
Page 119
... Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return Note 1: of actual I/O pin values. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 The TRISA register (Register 12-4) controls the PORTA pin output drivers, even when they are being used as analog inputs ...
Page 120
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATA4 LATA3 LATA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) (1) Preliminary R/W-1/1 R/W-1/1 TRISA1 TRISA0 bit 0 R/W-x/u R/W-x/u LATA1 LATA0 bit 0 © 2009 Microchip Technology Inc. ...
Page 121
... Unimplemented: Read as ‘0’ Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. Note 1: The weak pull-up device is automatically disabled if the pin is in configured as an output. 2: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 U-0 U-0 U-0 — ...
Page 122
... Pins configured as analog inputs will read ‘0’. R/W-1/1 R/W-1/1 R/W-1/1 ANSA4 ANSA3 ANSA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) . Digital input buffer disabled. Preliminary R/W-1/1 R/W-1/1 ANSA1 ANSA0 bit 0 © 2009 Microchip Technology Inc. ...
Page 123
... SRQ (SR Latch) 2. CCP3 (PIC16F/LF1827 only) 3. C1OUT (Comparator) 4. RA3 RA4 1. SRNQ (SR Latch) 2. CCP4 (PIC16F/LF1827 only) 3. T0CKI 4. C2OUT (Comparator) 5. RA4 © 2009 Microchip Technology Inc. PIC16F/LF1826/27 RA5 Input only pin. RA6 1. OSC2 (enabled by Configuration Word) 2. CLKOUT 3. CLKR 4. SDO1 5. P1D 6. P2B (PIC16F/LF1827 only) 7. RA6 RA7 1 ...
Page 124
... FOSC2 Preliminary Register Bit 1 Bit 0 on Page ANSA1 ANSA0 122 LATA1 LATA0 120 PS1 PS0 175 RA1 RA0 119 TRISA1 TRISA0 120 — — — 121 Register Bit 9/1 Bit 8/0 on Page BOREN0 CPD 50 FOSC1 FOSC0 © 2009 Microchip Technology Inc. ...
Page 125
... The ANSELB register must be initialized to Note: configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 12.3.1 WEAK PULL-UPS Each of the PORTB pins has an individually configurable internal weak pull-up. Control bits WPUB<7:0> enable or ...
Page 126
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATB4 LATB3 LATB2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/x R/W-x/x RB1 RB0 bit 0 R/W-1/1 R/W-1/1 TRISB1 TRISB0 bit 0 R/W-x/u R/W-x/u LATB1 LATB0 bit 0 © 2009 Microchip Technology Inc. ...
Page 127
... Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. Note 1: The weak pull-up device is automatically disabled if the pin is in configured as an output. 2: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 R/W-1/1 R/W-1/1 R/W-1/1 WPUB4 WPUB3 WPUB2 U = Unimplemented bit, read as ‘ ...
Page 128
... Pins configured as analog inputs will read ‘0’. R/W-1/1 R/W-1/1 R/W-1/1 ANSB4 ANSB3 ANSB2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) . Digital input buffer disabled. Preliminary R/W-1/1 U-0 ANSB1 — bit 0 © 2009 Microchip Technology Inc. ...
Page 129
... LATB6 OPTION_REG WPUEN INTEDG PORTB RB7 RB6 TRISB TRISB7 TRISB6 WPUB WPUB7 WPUB6 = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. — Legend: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 RB3 1. MDOUT 2. CCP1/P1A 3. RB3 RB4 1. SCL1 2. SCK1 3. RB4 RB5 1 ...
Page 130
... PIC16F/LF1826/27 NOTES: DS41391B-page 130 Preliminary © 2009 Microchip Technology Inc. ...
Page 131
... IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCBFx bits. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 13.4 Clearing Interrupt Flags The individual status flags, (IOCBFx bits), can be cleared by resetting them to zero ...
Page 132
... R/W/HS-0/0 IOCBF4 IOCBF3 IOCBF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HS = Bit is set by hardware Preliminary R/W-0/0 R/W-0/0 IOCBP1 IOCBP0 bit 0 R/W-0/0 R/W-0/0 IOCBN1 IOCBN0 bit 0 R/W/HS-0/0 R/W/HS-0/0 IOCBF1 IOCBF0 bit 0 © 2009 Microchip Technology Inc. ...
Page 133
... IOCBN7 IOCBN6 IOCBP IOCBP7 IOCBP6 TRISB TRISB7 TRISB6 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by interrupt-on-change. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 IOCBFx From all other IOCBFx individual pin detectors Q2 Clock Cycle Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 134
... PIC16F/LF1826/27 NOTES: DS41391B-page 134 Preliminary © 2009 Microchip Technology Inc. ...
Page 135
... FVRCON register. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> FVREN FVRRDY © 2009 Microchip Technology Inc. PIC16F/LF1826/27 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two independent programmable gain amplifiers. Each , with 1 ...
Page 136
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition ( Bit 5 Bit 4 Bit 3 Bit 2 Reserved Reserved CDAFVR1 CDAFVR0 Preliminary R/W-0/0 R/W-0/0 ADFVR1 ADFVR0 bit 0 (2) (2) (2) (2) Register Bit 1 Bit 0 on page ADFVR1 ADFVR0 136 © 2009 Microchip Technology Inc. ...
Page 137
... AN10 AN11 DAC FVR Buffer1 CHS<4:0> When ADON = 0, all multiplexer inputs are disconnected. Note: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) allows ADNREF = 1 ...
Page 138
... Table 15-1 gives examples of appro- priate ADC clock selections. Unless using the F Note: system clock frequency will change the ADC adversely affect the ADC result. Preliminary peri- AD specifica any changes in the RC clock frequency, which may © 2009 Microchip Technology Inc. ...
Page 139
... Sleep. FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit © 2009 Microchip Technology Inc. PIC16F/LF1826/ DEVICE OPERATING FREQUENCIES AD S Device Frequency (F Device Frequency (F 20 MHz 16 MHz (2) (2) (2) 100 ns 125 ns (2) (2) (2) 200 ns ...
Page 140
... ADCON1 register controls the output format. Figure 15-3 shows the two output formats. ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result Preliminary ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 © 2009 Microchip Technology Inc. ...
Page 141
... A device Reset forces all registers to their Note: Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 15.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...
Page 142
... MOVF ADRESL,W MOVWF RESULTLO Preliminary A/D CONVERSION ; ;clock ;Vdd and Vss Vref ; ;Set RA0 to input ; ;Set RA0 to analog ; ;Turn ADC On ;Acquisiton delay ;No, test again ; ;Read upper 2 bits ;store in GPR space ; ;Read lower 8 bits ;Store in GPR space © 2009 Microchip Technology Inc. ...
Page 143
... ADC is enabled 0 = ADC is disabled and consumes no operating current See Section 16.0 “Digital-to-Analog Converter (DAC) Module” for more information. Note 1: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information. 2: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 R/W-0/0 R/W-0/0 R/W-0/0 CHS2 ...
Page 144
... REF DS41391B-page 144 R/W-0/0 U-0 R/W-0/0 ADCS0 — ADNREF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets SS - REF DD + REF Preliminary R/W-0/0 R/W-0/0 ADPREF1 ADPREF0 bit 0 © 2009 Microchip Technology Inc. ...
Page 145
... Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 R/W-x/u R/W-x/u R/W-x/u ADRES6 ADRES5 ADRES4 U = Unimplemented bit, read as ‘0’ ...
Page 146
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u ADRES4 ADRES3 ADRES2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u ADRES9 ADRES8 bit 0 R/W-x/u R/W-x/u ADRES1 ADRES0 bit 0 © 2009 Microchip Technology Inc. ...
Page 147
... REF 2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...
Page 148
... V SS DS41391B-page 148 V DD Sampling Switch ≈ 0. Rss R ≤ LEAKAGE ( ≈ 0. Full-Scale Range 1 LSB ideal Full-Scale Transition Analog Input Voltage 1 LSB ideal Zero-Scale V REF Transition Preliminary HOLD REF Sampling Switch (kΩ) © 2009 Microchip Technology Inc. ...
Page 149
... FVRRDY DACCON0 DACEN DACLPS DACCON1 — — — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. Legend: * Page provides register information. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 CHS3 CHS2 CHS1 CHS0 ADCS1 ADCS0 — ...
Page 150
... PIC16F/LF1826/27 NOTES: DS41391B-page 150 Preliminary © 2009 Microchip Technology Inc. ...
Page 151
... Either the positive voltage source, (V negative voltage source can be disabled. SRC © 2009 Microchip Technology Inc. PIC16F/LF1826/27 The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the DACLPS bit in the DACCON0 register disables the positive voltage source ...
Page 152
... VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41391B-page 152 Digital-to-Analog Converter (DAC SRC Steps SRC + DACOUT – Preliminary DACR<4:0> 5 DAC (To Comparator and ADC Modules) DACOUT DACOE Buffered DAC Output © 2009 Microchip Technology Inc. ...
Page 153
... Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DAC1R<4:0> range select bits are cleared. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Preliminary DS41391B-page 153 ...
Page 154
... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 DACR4 DACR3 DACR2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets 5 -))*(DACR<4:0>/( SRC Preliminary U-0 R/W-0/0 — DACNSS bit 0 R/W-0/0 R/W-0/0 DACR1 DACR0 bit 0 © 2009 Microchip Technology Inc. ...
Page 155
... Bit 7 Bit 6 FVRCON FVREN FVRRDY DACCON0 DACEN DACLPS DACCON1 — — — = unimplemented, read as ‘0’. Shaded cells are unused by the DAC module. Legend: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 Reserved Reserved CDAFVR1 CDAFVR0 DACOE — DACPSS1 DACPSS0 — ...
Page 156
... PIC16F/LF1826/27 NOTES: DS41391B-page 156 Preliminary © 2009 Microchip Technology Inc. ...
Page 157
... V -, the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN © 2009 Microchip Technology Inc. PIC16F/LF1826/27 FIGURE 17-1: SINGLE COMPARATOR – V ...
Page 158
... DS41391B-page 158 (1) Interrupt Interrupt C POL CxHYS D (from Timer1) T1CLK Preliminary CxINTP det Set CxIF CxINTN det C OUT X To Data Bus Q MC OUT X To ECCP PWM Logic C SYNC TRIS bit C OUT Timer1 and SR Latch SYNCC OUT X © 2009 Microchip Technology Inc. ...
Page 159
... FVR Buffer2 3 CxON PCH<1:0> When CxON = 0, the Comparator will produce a ‘0’ at the output Note 1: When CxON = 0, all multiplexer inputs are disconnected. 2: Output of comparator can be frozen during debugging. 3: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 (1) Interrupt Interrupt C POL CxHYS D (from Timer1) ...
Page 160
... CxSP control bit. The default state for this bit is ‘1’ which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propaga- tion delay by clearing the CxSP bit to ‘0’. Preliminary © 2009 Microchip Technology Inc. CxOUT ...
Page 161
... Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 17-2) and the Timer1 Block Diagram (Figure 20-1) for more information. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 17.5 Comparator Interrupt An interrupt can be generated upon a change in the ...
Page 162
... Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified ≈ 0. (1) LEAKAGE ≈ 0. Vss Preliminary and V . The DD SS and Comparator © 2009 Microchip Technology Inc. ...
Page 163
... CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on the Timer1 clock source. Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous © 2009 Microchip Technology Inc. PIC16F/LF1826/27 R/W-0/0 U-0 ...
Page 164
... Value at POR and BOR/Value at all other Resets DAC SS U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 CxNCH1 CxNCH0 bit 0 R-0/0 R-0/0 MC2OUT MC1OUT bit 0 © 2009 Microchip Technology Inc. ...
Page 165
... C2IF PIR2 PORTA RA7 RA6 TRISA TRISA7 TRISA6 — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. Legend: PIC16F/LF1827 only. Note 1: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 ANSA3 ANSA2 CxOE CxPOL — ...
Page 166
... PIC16F/LF1826/27 NOTES: DS41391B-page 166 Preliminary © 2009 Microchip Technology Inc. ...
Page 167
... Enabling both the Set and Reset inputs Note: from any one source at the same time may result in indeterminate operation, as the Reset dominance cannot be assured. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 18.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs ...
Page 168
... SRRPE SRCLK SRRCKE (3) SYNCC2OUT SRRC2E (3) SYNCC1OUT SRRC1E and simultaneously Note 1: Pulse generator causes a 1 Q-state pulse width. 2: Name denotes the connection point at the comparator output. 3: DS41391B-page 168 SRLEN SRQEN (1) Latch R Q SRLEN SRNQEN Preliminary © 2009 Microchip Technology Inc. SRQ SRNQ ...
Page 169
... Pulse set input for 1 Q-clock period effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 = Pulse reset input for 1 Q-clock period effect on reset input. Set only, always reads back ‘0’. Note 1: © 2009 Microchip Technology Inc. PIC16F/LF1826/ MHz MHz OSC OSC 39 ...
Page 170
... C1 Comparator output has no effect on the reset input of the SR Latch DS41391B-page 170 R/W-0/0 R/W-0/0 R/W-0/0 SRSC1E SRRPE SRRCKE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 SRRC2E SRRC1E bit 0 © 2009 Microchip Technology Inc. ...
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... SRCON0 SRLEN SRCLK2 SRCON1 SRSPE SRSCKE TRISA TRISA7 TRISA6 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the SR Latch module. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 ANSA3 ANSA2 SRCLK1 SRCLK0 SRQEN ...
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... PIC16F/LF1826/27 NOTES: DS41391B-page 172 Preliminary © 2009 Microchip Technology Inc. ...
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... From CPSCLK 1 TMR0CS TMR0SE T0XCS © 2009 Microchip Technology Inc. PIC16F/LF1826/27 When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. The value written to the TMR0 register can Note: be adjusted, in order to account for the two instruction cycle delay when TMR0 is written ...
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... Section 29.0 “Electrical Specifications”. 19.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41391B-page 174 Preliminary © 2009 Microchip Technology Inc. ...
Page 175
... Timer0 Module Register TRISA TRISA7 TRISA6 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ ...
Page 176
... PIC16F/LF1826/27 NOTES: DS41391B-page 176 Preliminary © 2009 Microchip Technology Inc. ...
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... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 • Gate Toggle Mode • Gate Single-pulse Mode • Gate Value Status • Gate Event Interrupt Figure 20 block diagram of the Timer1 module ...
Page 178
... Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. T1OSCEN System Clock (F ) OSC x Instruction Clock (F OSC x Capacitive Sensing Oscillator x External Clocking on T1CKI Pin 0 Osc.Circuit On T1OSI/T1OSO Pins 1 Preliminary system clock or they can run Clock Source /4) © 2009 Microchip Technology Inc. ...
Page 179
... A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 20.6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry ...
Page 180
... TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). Preliminary © 2009 Microchip Technology Inc. ...
Page 181
... T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 20.9 ECCP/CCP Capture/Compare Time Base The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...
Page 182
... PIC16F/LF1826/27 FIGURE 20-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL TIMER1 N FIGURE 20-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL TIMER1 DS41391B-page 182 Preliminary © 2009 Microchip Technology Inc ...
Page 183
... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N Cleared by software TMR1GIF © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41391B-page 183 ...
Page 184
... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N Cleared by software TMR1GIF DS41391B-page 184 Set by hardware on falling edge of T1GVAL Preliminary © 2009 Microchip Technology Inc. Cleared by hardware on falling edge of T1GVAL Cleared by software ...
Page 185
... This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop © 2009 Microchip Technology Inc. PIC16F/LF1826/27 R/W-0/u R/W-0/u R/W-0/u T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ...
Page 186
... Comparator 2 optionally synchronized output (SYNCC2OUT) DS41391B-page 186 R/W-0/u R/W/HC-0/u R-x/x T1GSPM T1GGO/ T1GVAL DONE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HC = Bit is cleared by hardware Preliminary R/W-0/u R/W-0/u T1GSS1 T1GSS0 bit 0 © 2009 Microchip Technology Inc. ...
Page 187
... TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC T1CON TMR1GE T1GPOL T1GCON Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 ANSB3 ...
Page 188
... PIC16F/LF1826/27 NOTES: DS41391B-page 188 Preliminary © 2009 Microchip Technology Inc. ...
Page 189
... Optional use as the shift clock for the MSSPx modules (Timer2 only) See Figure 21-1 for a block diagram of Timer2/4/6. FIGURE 21-1: TIMER2/4/6 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 TxCKPS<1:0> © 2009 Microchip Technology Inc. PIC16F/LF1826/27 TMRx Output Reset TMRx Postscaler Comparator 1 PRx TxOUTPS< ...
Page 190
... Timer2/4/6 Operation During Sleep The Timerx timers cannot be operated while the the output processor is in Sleep mode. The contents of the TMRx and PRx registers will remain unchanged while the processor is in Sleep mode. the 4-bit Preliminary © 2009 Microchip Technology Inc. ...
Page 191
... TMRxON: Timerx On bit 1 = Timerx Timerx is off bit 1-0 TxCKPS<1:0>: Timer2-type Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler Prescaler is 64 © 2009 Microchip Technology Inc. PIC16F/LF1826/27 R/W-0/0 R/W-0/0 R/W-0/0 TxOUTPS1 TxOUTPS0 TMRxON U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 192
... TMR2ON (1) TMR4ON (1) TMR6ON Preliminary Register Bit 1 Bit 0 on Page INTF IOCIF 89 TMR2IE TMR1IE 90 TMR2IF TMR1IF 94 — TMR4IE — 92 — TMR4IF — 96 189* 189* T2CKPS1 T2CKPS0 191 189* 189* T4CKPS1 T4CKPS0 191 189* 189* T6CKPS1 T6CKPS0 191 © 2009 Microchip Technology Inc. ...
Page 193
... Reserved * No Channel * Selected 1111 © 2009 Microchip Technology Inc. PIC16F/LF1826/27 Using this method, the DSM can generate the following types of Key Modulation schemes: • Frequency-Shift Keying (FSK) • Phase-Shift Keying (PSK) • On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: • ...
Page 194
... MDCHSYNC bit in the MDCARH register. Synchroniza- tion for the carrier low signal can be enabled by setting the MDCLSYNC bit in the MDCARL register. Figure 22-1 through Figure 22-5 show timing diagrams of using various synchronization methods. Preliminary © 2009 Microchip Technology Inc. ...
Page 195
... Active Carrier State FIGURE 22-3: CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 CARH Active Carrier State © 2009 Microchip Technology Inc. PIC16F/LF1826/27 CARL CARH CARH CARL both Preliminary CARL both CARL DS41391B-page 195 ...
Page 196
... Active Carrier CARH State FIGURE 22-5: FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling edges used to sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier CARH State DS41391B-page 196 CARL CARH CARL CARH Preliminary © 2009 Microchip Technology Inc. CARL CARL ...
Page 197
... The DSM module is not affected by Sleep mode. The DSM can still operate during Sleep, if the Carrier and Modulator input sources are also still operable during Sleep. © 2009 Microchip Technology Inc. PIC16F/LF1826/27 22.12 Effects of a Reset Upon any device Reset, the data signal modulator module is disabled. The user’ ...
Page 198
... DS41391B-page 198 R/W-0/0 U-0 U-0 MDOPOL MDOUT — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (2) Preliminary U-0 R/W-0/0 — MDBIT bit 0 (1) © 2009 Microchip Technology Inc. ...
Page 199
... CCP1 output (PWM Output mode only) 0001 = MDMIN port pin 0000 = MDBIT bit of MDCON register is modulation source Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. Note 1: © 2009 Microchip Technology Inc. PIC16F/LF1826/27 U-0 R/W-x/u R/W-x/u — ...
Page 200
... Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. Note 1: DS41391B-page 200 U-0 R/W-x/u R/W-x/u — MDCH3 MDCH2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary © 2009 Microchip Technology Inc. R/W-x/u R/W-x/u MDCH1 MDCH0 bit 0 (1) ...