ATMEGA168PA-PU Atmel, ATMEGA168PA-PU Datasheet - Page 287

• Manufacturer Part Number: ATMEGA168PA-PU
• Description: MCU, 8BIT, AVR, 16K FLASH, 28PDIP
• Manufacturer: Atmel

Specifications of ATMEGA168PA-PU

• Controller Family/series: Atmega
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 16KB
• Oscillator Type: External, Internal
• Rohs Compliant: Yes

26.8.10
8271C–AVR–08/10
Reading the Signature Row from Software
instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set
in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET
and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM
instruction is executed within three CPU cycles or no SPM instruction is executed within four
CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the
Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles
after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte
(FLB) will be loaded in the destination register as shown below. Refer to
for a detailed description and mapping of the Fuse Low byte.
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the
SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as
shown below. Refer to
High byte.
When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction
is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR,
the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown
below. Refer to
Fuse byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
To read the Signature Row from software, load the Z-pointer with the signature byte address
given in
LPM instruction is executed within three CPU cycles after the SIGRD and SPMEN bits are set in
SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD and
SPMEN bits will auto-clear upon completion of reading the Signature Row Lock bits or if no LPM
instruction is executed within three CPU cycles. When SIGRD and SPMEN are cleared, LPM will
work as described in the Instruction set Manual.
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Bit
Rd
Bit
Rd
Bit
Rd
Bit
Rd
Table 26-5 on page 288
FHB7
FLB7
Table 27-5 on page 298
7
7
7
–
7
–
Table 27-7 on page 298
FHB6
FLB6
6
6
6
–
6
–
BLB12
FHB5
and set the SIGRD and SPMEN bits in SPMCSR. When an
FLB5
5
5
5
–
5
for detailed description and mapping of the Extended
BLB11
FHB4
FLB4
4
4
4
4
–
for detailed description and mapping of the Fuse
BLB02
FLB3
FHB3
EFB3
3
3
3
3
BLB01
FHB2
EFB2
FLB2
2
2
2
2
FLB1
FHB1
EFB1
LB2
Table 27-5 on page 298
1
1
1
1
FLB0
FHB0
EFB0
LB1
0
0
0
0
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