LPC2212FBD144 NXP Semiconductors, LPC2212FBD144 Datasheet
LPC2212FBD144
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LPC2212/2214 16/32-bit ARM microcontrollers; 128/256 kB ISP/IAP flash with 10-bit ADC and external memory interface Rev. 04 — 3 January 2008 1. General description The LPC2212/2214 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, ...
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... I Dual power supply: N CPU operating voltage range of 1. 1. I/O power supply range of 3 3 Ordering information Table 1. Type number LPC2212FBD144 LPC2212FBD144/00 LPC2212FBD144/01 LPC2214FBD144 LPC2214FBD144/00 LPC2214FBD144/01 LPC2212_2214_4 Product data sheet Ordering information Package Name Description LQFP144 plastic low profile quad flat package; 144 leads; ...
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... NXP Semiconductors 3.1 Ordering options Table 2. Type number LPC2212FBD144 LPC2212FBD144/00 LPC2212FBD144/01 LPC2214FBD144 LPC2214FBD144/00 LPC2214FBD144/01 LPC2212_2214_4 Product data sheet Ordering options Flash memory 128 kB 128 kB 128 kB 256 kB 256 kB 256 kB Rev. 04 — 3 January 2008 LPC2212/2214 16/32-bit ARM microcontrollers RAM Fast GPIO/ Temperature range ...
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... NXP Semiconductors 4. Block diagram LPC2212 LPC2214 HIGH-SPEED (3) P0, P1 GPI/O 48 PINS TOTAL ARM7 LOCAL BUS INTERNAL SRAM CONTROLLER 16 kB SRAM EXTERNAL (1) EINT[3:0] INTERRUPTS (1) 4 CAP0 CAPTURE/ (1) 4 CAP1 COMPARE (1) 4 MAT0 TIMER 0/TIMER 1 (1) 4 MAT1 (1) AIN[3:0] A/D CONVERTER (1) AIN[7:4] P0[30:27], P0[25:0] P1[31:16], ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning (1) Pin configuration is identical for devices with and without /00 and /01 suffixes. Fig 2. Pin configuration (LQFP144) LPC2212_2214_4 Product data sheet 1 LPC2212 (1) LPC2214 36 Rev. 04 — 3 January 2008 LPC2212/2214 16/32-bit ARM microcontrollers 108 73 002aad182 © NXP B.V. 2008. All rights reserved. ...
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... NXP Semiconductors 5.2 Pin description Table 3. Pin description Symbol Pin P0[0] to P0[31] P0[0]/TXD0/PWM1 42 P0[1]/RXD0/PWM3/ 49 EINT0 P0[2]/SCL/CAP0[0] 50 P0[3]/SDA/MAT0[0]/ 58 EINT1 P0[4]/SCK0/CAP0[1] 59 P0[5]/MISO0/MAT0[1] 61 P0[6]/MOSI0/CAP0[2] 68 P0[7]/SSEL0/PWM2/ 69 EINT2 P0[8]/TXD1/PWM4 75 P0[9]/RXD1/PWM6/ 76 EINT3 P0[10]/RTS1/CAP1[0] 78 P0[11]/CTS1/CAP1[1] 83 P0[12]/DSR1/MAT1[0] ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin P0[14]/DCD1/EINT1 92 P0[15]/RI1/EINT2 99 P0[16]/EINT0/MAT0[2]/ 100 CAP0[2] P0[17]/CAP1[2]/SCK1/ 101 MAT1[2] P0[18]/CAP1[3]/MISO1/ 121 MAT1[3] P0[19]/MAT1[2]/MOSI1/ 122 CAP1[2] P0[20]/MAT1[3]/SSEL1/ 123 EINT3 P0[21]/PWM5/CAP1[3] 4 P0[22]/CAP0[0]/MAT0[0] 5 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin P0[30]/AIN3/EINT3/ 33 CAP0[0] P1[0] to P1[31] P1[0]/CS0 91 P1[1]/OE 90 P1[16]/TRACEPKT0 34 P1[17]/TRACEPKT1 24 P1[18]/TRACEPKT2 15 P1[19]/TRACEPKT3 7 P1[20]/TRACESYNC 102 P1[21]/PIPESTAT0 95 P1[22]/PIPESTAT1 86 P1[23]/PIPESTAT2 82 P1[24]/TRACECLK 70 P1[25]/EXTIN0 60 P1[26]/RTCK 52 P1[27]/TDO ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin P2[7]/D7 116 P2[8]/D8 117 P2[9]/D9 118 P2[10]/D10 120 P2[11]/D11 124 P2[12]/D12 125 P2[13]/D13 127 P2[14]/D14 129 P2[15]/D15 130 P2[16]/D16 131 P2[17]/D17 132 P2[18]/D18 133 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin P3[3]/A3 81 P3[4]/A4 80 P3[5]/A5 74 P3[6]/A6 73 P3[7]/A7 72 P3[8]/A8 71 P3[9]/A9 66 P3[10]/A10 65 P3[11]/A11 64 P3[12]/A12 63 P3[13]/A13 62 P3[14]/A14 56 P3[15]/A15 55 P3[16]/A16 53 P3[17]/A17 48 P3[18]/A18 47 P3[19]/A19 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin 26, SS 38, 54, 67, 79, 93, 103, 107, 111, 128 V 139 SSA V 138 SSA(PLL) V 37, 110 DD(1V8) V 143 DDA(1V8 31, 39, DD(3V3) 51, 57, 77, 94, 104, 112, 119 V 14 DDA(3V3) [1] SSP interface is available on LPC2212/01 and LPC2214/01 only. LPC2212_2214_4 ...
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... NXP Semiconductors 6. Functional description Details of the LPC2212/2214 systems and peripheral functions are described in the following sections. 6.1 Architectural overview The ARM7TDMI general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers ...
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... NXP Semiconductors time (no matter whether the CRP off). Removal of CRP is achieved by erasure of full on-chip user flash. With the CRP off, full access to the chip via the JTAG and/or ISP is restored. 6.3 On-chip static RAM On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8 bit, 16 bit, and 32 bit ...
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... NXP Semiconductors Fig 3. LPC2212/2214 memory map 6.5 Interrupt controller The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt reQuest (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... NXP Semiconductors Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. ...
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... NXP Semiconductors [1] SSP interface available on LPC2212/01 and LPC2214/01 only. 6.6 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled ...
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... NXP Semiconductors 6.9 10-bit ADC The LPC2212/2214 each contain a single 10-bit successive approximation ADC with four multiplexed channels. 6.9.1 Features • Measurement range • Capable of performing more than 400000 10-bit samples per second. • Burst conversion mode for single or multiple inputs. ...
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... NXP Semiconductors 2 6.11 I C-bus serial I/O controller 2 The I C-bus is a bidirectional bus for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter with the capability to both receive and send information (such as memory) ...
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... NXP Semiconductors • When the SPI interface is used in Master mode, the SSEL pin is not needed (can be used for a different function). 6.13 SSP controller (LPC2212/2214/01 only) The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. Data transfers are in principle full duplex, with frames of four to 16 bits of data fl ...
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... NXP Semiconductors – Toggle on match. – Do nothing on match. 6.14.2 Features available in LPC2212/2214/01 only The LPC2212/2214/01 can count external events on one of the capture inputs if the external pulse lasts at least one half of the period of the PCLK. In this configuration, unused capture lines can be selected as regular timer capture inputs, or used as external interrupts. • ...
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... NXP Semiconductors • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Programmable reference clock divider allows adjustment of the RTC to match various crystal frequencies. 6.17 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2212/2214 ...
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... NXP Semiconductors • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • ...
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... NXP Semiconductors functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the Wake-up Timer. The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution ...
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... NXP Semiconductors 6.18.6 Memory mapping control The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip flash memory the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts ...
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... NXP Semiconductors The ARM core has a Debug Communication Channel function built-in. The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The debug communication channel is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core ...
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... NXP Semiconductors 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply voltage (3.3 V) DDA(3V3) V analog input voltage IA V input voltage I I supply current DD I ground current ...
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... NXP Semiconductors 8. Static characteristics Table 6. Static characteristics +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply voltage DDA(3V3) (3.3 V) Standard port pins, RESET, RTCK I LOW-level input current IL I HIGH-level input current ...
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... NXP Semiconductors Table 6. Static characteristics +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter Power consumption LPC2212/01 and LPC2214/01 I active mode supply current DD(act) I Idle mode supply current DD(idle) I Power-down mode supply DD(pd) current 2 I C-bus pins V HIGH-level input voltage ...
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... NXP Semiconductors Table 7. ADC static characteristics 3.6 V unless otherwise specified; T DDA 4.5 MHz. Symbol Parameter V analog input voltage IA C analog input ia capacitance E differential linearity D error E integral non-linearity L(adj) E offset error O E gain error G E absolute error T [1] Conditions 3.3 V. ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 4. ADC characteristics LPC2212_2214_4 Product data sheet ...
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... NXP Semiconductors 8.1 Power consumption measurements for LPC2212/01 and LPC2214/01 The power consumption measurements represent typical values for the given conditions. The peripherals were enabled through the PCONP register, but for these measurements, the peripherals were not configured to run. Peripherals were disabled through the PCONP register ...
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... NXP Semiconductors 45 I DD(act) (mA 1.65 Test conditions: Active mode entered executing code from on-chip flash; PCLK = Temp = 25 C; core voltage 1.8 V; all peripherals disabled. Fig 7. Typical LPC2212/01 and LPC2214/ DD(idle) (mA Test conditions: Idle mode entered executing code from on-chip flash; PCLK = ...
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... NXP Semiconductors 8 I DD(idle) (mA 1.65 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals enabled. amb Fig 9. Typical LPC2212/01 and LPC2214/ DD(idle) (mA 1.65 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = Temp = 25 C ...
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... NXP Semiconductors 45 I DD(act) (mA -40 -15 Test conditions: Active mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V; all peripherals disabled. Fig 11. Typical LPC2212/01 and LPC2214/01 I 6.0 I DD(idle) (mA) 5.0 4.0 3.0 2.0 1.0 -40 -15 Test conditions: Idle mode entered executing code from on-chip flash; PCLK = core voltage 1.8 V ...
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... NXP Semiconductors 200 I DD(pd 160 120 -40 -15 Test conditions: Power-down mode entered executing code from on-chip flash. Fig 13. Typical LPC2212/01 and LPC2214/01 core power-down current I Table 8. Core voltage 1 Peripheral Timer0 Timer1 UART0 UART1 PWM0 2 I C-bus SPI0/1 RTC ADC EMC LPC2212_2214_4 ...
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... NXP Semiconductors 9. Dynamic characteristics Table 9. Dynamic characteristics +85 C for industrial applications; V amb Symbol Parameter External clock f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX t clock rise time CLCH t clock fall time CHCL Port pins (except P0[2] and P0[3]) ...
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... NXP Semiconductors Table 10. External memory interface dynamic characteristics pF amb Symbol Parameter Common to read and write cycles t XCLK HIGH to address valid CHAV time t XCLK HIGH to CS LOW time CHCSL t XCLK HIGH to CS HIGH CHCSH time t XCLK HIGH to address CHANV invalid time Read cycle parameters ...
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... NXP Semiconductors Table 10. External memory interface dynamic characteristics pF amb Symbol Parameter t BLS HIGH to data invalid BLSHDNV time t XCLK HIGH to data valid CHDV time t XCLK HIGH to WE LOW CHWEL time t XCLK HIGH to BLS LOW CHBLSL time t XCLK HIGH to WE HIGH CHWEH time ...
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... NXP Semiconductors 9.1 Timing XCLK CS addr data t CSLOEL OE Fig 14. External memory read access XCLK CS BLS/WE addr data OE Fig 15. External memory write access LPC2212_2214_4 Product data sheet t CSLAV OELAV t CHOEL t CSLDV t AVCSL t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV t CSLDV Rev. 04 — 3 January 2008 ...
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... NXP Semiconductors V Fig 16. External clock timing LPC2212_2214_4 Product data sheet 0 0.2V 0 0. CHCL Rev. 04 — 3 January 2008 LPC2212/2214 16/32-bit ARM microcontrollers t CHCX t t CLCX CLCH T cy(clk) 002aaa907 © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors 10. Package outline LQFP144: plastic low profile quad flat package; 144 leads; body 1 108 109 pin 1 index 144 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 11. Abbreviations Table 12. Acronym ADC AMBA APB CPU DCC EMC FIFO GPIO JTAG PLL POR PWM RAM SPI SRAM SSI SSP TTL UART LPC2212_2214_4 Product data sheet Abbreviations Description Analog-to-Digital Converter Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Central Processing Unit ...
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... NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Type number LPC2212FBD144/01 has been added. • Type number LPC2214FBD144/01 has been added. • Details introduced with /01 devices on new peripherals/features (Fast I/O Ports, SSP, CRP) and enhancements to existing ones (UART0/1, Timers, ADC, and SPI) added. • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features brought by LPC2212/2214/01 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Key features common for all devices . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . 12 6.1 Architectural overview ...