ST62T62CB6 STMicroelectronics, ST62T62CB6 Datasheet - Page 31

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ST62T62CB6

Manufacturer Part Number
ST62T62CB6
Description
8BIT MCU OTP 2K+EEPROM, 62T62, DIP
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST62T62CB6

Controller Family/series
ST6
No. Of I/o's
9
Eeprom Memory Size
64Byte
Ram Memory Size
128Byte
Cpu Speed
8MHz
No. Of
RoHS Compliant
Core Size
8bit
Program Memory Size
1836B
Oscillator Type
External Only
Processor Series
ST62T6x
Core
ST6
Data Bus Width
8 bit
Program Memory Type
EPROM
Data Ram Size
128 B
Interface Type
SPI, UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
9
Number Of Timers
2
Operating Supply Voltage
3 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-16
Development Tools By Supplier
ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / Rohs Status
 Details

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0
INTERRUPTS (Cont’d)
3.4.2 Interrupt Procedure
The interrupt procedure is very similar to a call pro-
cedure, indeed the user can consider the interrupt
as an asynchronous call procedure. As this is an
asynchronous event, the user cannot know the
context and the time at which it occurred. As a re-
sult, the user should save all Data space registers
which may be used within the interrupt routines.
There are separate sets of processor flags for nor-
mal, interrupt and non-maskable interrupt modes,
which are automatically switched and so do not
need to be saved.
The following list summarizes the interrupt proce-
dure:
MCU
– The interrupt is detected.
– The C and Z flags are replaced by the interrupt
– The PC contents are stored in the first level of
– The normal interrupt lines are inhibited (NMI still
– The first internal latch is cleared.
– The associated interrupt vector is loaded in the PC.
WARNING: In some circumstances, when a
maskable interrupt occurs while the ST6 core is in
NORMAL mode and especially during the execu-
tion of an "ldi IOR, 00h" instruction (disabling all
maskable interrupts): if the interrupt arrives during
the first 3 cycles of the "ldi" instruction (which is a
4-cycle instruction) the core will switch to interrupt
mode BUT the flags CN and ZN will NOT switch to
the interrupt pair CI and ZI.
User
– User selected registers are saved within the in-
– The source of the interrupt is found by polling the
– The interrupt is serviced.
– Return from interrupt (RETI)
flags (or by the NMI flags).
the stack.
active).
terrupt service routine (normally on a software
stack).
interrupt flags (if more than one source is associ-
ated with the same vector).
MCU
– Automatically the MCU switches back to the nor-
The interrupt routine usually begins by the identify-
ing the device which generated the interrupt re-
quest (by polling). The user should save the regis-
ters which are used within the interrupt routine in a
software stack. After the RETI instruction is exe-
cuted, the MCU returns to the main routine.
Figure 20. Interrupt Processing Flow Chart
mal flag set (or the interrupt flag set) and pops
the previous PC value from the stack.
YES
NO
PROGRAM FLAGS
THE INSTRUCTION
INTERRUPT MASK
THE STACKED PC
INSTRUCTION
INSTRUCTION
INSTRUCTION
EXECUTE
A RETI
SELECT
WAS
FETCH
CLEAR
"POP"
?
?
YES
NO
YES
?
ST62T52C ST62T62C/E62C
AN INTERRUPT REQUEST
NO
NORMAL MODE?
AND INTERRUPT MASK
IS THE CORE
ALREADY IN
CHECK IF THERE IS
INTERNAL MODE FLAG
PC INTO THE STACK
INTERRUPT VECTOR
INTERRUPT MASK
LOAD PC FROM
PUSH THE
(FFC/FFD)
SELECT
SET
VA000014
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