UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 177

8BIT UC, 32K FLASH, 1KB RAM, LCD

UPD78F0413GA-GAM-AX

Manufacturer Part Number
UPD78F0413GA-GAM-AX
Description
8BIT UC, 32K FLASH, 1KB RAM, LCD
Manufacturer
NEC
Datasheet

Specifications of UPD78F0413GA-GAM-AX

Controller Family/series
UPD78F
No. Of I/o's
30
Ram Memory Size
1024Byte
Cpu Speed
10MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
32KB
Oscillator Type
External, Internal

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This is an application example where the pulse width of the signal input to the TI000 pin is measured.
By setting CRC00, the count value can be captured to CR000 in the phase reverse to the falling edge of the
TI000 pin (i.e., rising edge) and to CR010 at the falling edge of the TI000 pin.
The high- and low-level widths of the input pulse can be calculated by the following expressions.
If the reverse phase of the TI000 pin is selected as a trigger to capture the count value to CR000, the INTTM000
signal is not generated. Read the values of CR000 and CR010 to measure the pulse width immediately after the
INTTM010 signal is generated.
However, if the valid edge specified by bits 6 and 5 (ES101 and ES100) of prescaler mode register 00 (PRM00) is
input to the TI010 pin, the count value is not captured but the INTTM000 signal is generated. To measure the
pulse width of the TI000 pin, mask the INTTM000 signal when it is not used.
High-level width = [CR010 value] – [CR000 value]
Low-level width = [CR000 value]
Capture & count clear input
Figure 6-30. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(TMC003, TMC002)
Capture interrupt
Capture interrupt
(TI000 pin input)
Capture register
Capture register
TM00 register
Operable bits
Capture input
(INTTM010)
(INTTM000)
(CR000)
(CR010)
(CR000: Capture Register, CR010: Capture Register) (3/3)
(TI010)
0000H
(c) TOC00 = 13H, PRM00 = 00H, CRC00 = 07H, TMC00 = 0AH
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
L
L
00
[Count clock cycle]
0000H
0000H
User’s Manual U18698EJ1V0UD
L
M
L
[Count clock cycle]
10
N
M
P
O
N
O
Q
P
R
Q
S
R
T
S
T
W
W
177

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