UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 210
UPD78F0413GA-GAM-AX
Manufacturer Part Number
UPD78F0413GA-GAM-AX
Description
8BIT UC, 32K FLASH, 1KB RAM, LCD
Manufacturer
NEC
Datasheet
1.UPD78F0413GA-GAM-AX.pdf
(562 pages)
Specifications of UPD78F0413GA-GAM-AX
Controller Family/series
UPD78F
No. Of I/o's
30
Ram Memory Size
1024Byte
Cpu Speed
10MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
32KB
Oscillator Type
External, Internal
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6.4.10 Cautions for external 24-bit event counter
(1) 8-bit timer counter H2 output signal
210
Note This setting is not required if input enable for the TI52 pin is not controlled.
The output level control (default value) of 8-bit timer H2 which is used to control input enable for the TI52 pin,
must be set to high level (TOLEV2 = 1). Consequently, an interrupt request signal (INTTMH2) is generated while
the input enable signal to the TI52 pin is disabled (TMH2 output: low level), and the TM52 and TM00 count values
(= external event count value in input enable period) can be read via servicing of this interrupt.
Note with caution that the input enable signal to the TI52 pin is at high level (enable status) until the TMH2 and
CMP02 register values match, after 8-bit timer H2 operation has been enabled (TMHE2 = 1) via this setting
(TOLEV2 = 1).
These operations must be restarted
since the counter is cleared when
timer operation is stopped.
TMC003 = 0, TMC002 = 0
Figure 6-56. Operation Flowchart of External 24-bit Event Counter
TCE52 = 0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
User’s Manual U18698EJ1V0UD
Set TM52 to external event counter
Starts TMH2 count operation
Starts TM00 count operation
Starts TM52 count operation
Starts TM00 count operation
Starts TM52 count operation
Set TM00 to interval timer
Read TM00 counter value
Read TM52 counter value
Clear TM00 counter value
Clear TM52 counter value
Set TMH2 to PWM mode
Generates INTTMH2?
Note
Note
Set in this order
Perform these steps during
low-level output of TOH2
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