UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 457
UPD78F0413GA-GAM-AX
Manufacturer Part Number
UPD78F0413GA-GAM-AX
Description
8BIT UC, 32K FLASH, 1KB RAM, LCD
Manufacturer
NEC
Datasheet
1.UPD78F0413GA-GAM-AX.pdf
(562 pages)
Specifications of UPD78F0413GA-GAM-AX
Controller Family/series
UPD78F
No. Of I/o's
30
Ram Memory Size
1024Byte
Cpu Speed
10MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
32KB
Oscillator Type
External, Internal
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19.1.2 Registers controlling standby function
(1) Oscillation stabilization time counter status register (OSTC)
The standby function is controlled by the following two registers.
Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1
clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock,
the X1 clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, and WDT), the STOP instruction and MSTOP (bit 7 of
MOC register) = 1 clear OSTC to 00H.
Address: FFA3H
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Symbol
OSTC
Figure 19-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Remark f
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
MOST11
7
0
1
1
1
1
1
After reset: 00H
2. The oscillation stabilization time counter counts up to the oscillation
3. The X1 clock oscillation stabilization wait time does not include the time until
X
: X1 clock oscillation frequency
MOST13
remain 1.
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
clock oscillation starts (“a” below).
6
0
0
1
1
1
1
X1 pin voltage
waveform
Desired OSTC oscillation stabilization time
set by OSTS
CHAPTER 19 STANDBY FUNCTION
R
MOST14
User’s Manual U18698EJ1V0UD
5
0
0
0
1
1
1
STOP mode release
MOST11
MOST15
4
0
0
0
1
1
a
MOST13
MOST16
3
0
0
0
0
1
2
2
2
2
2
11
13
14
15
16
MOST14
Oscillation stabilization time status
/f
/f
/f
/f
/f
X
X
X
X
X
2
min.
min.
min.
min.
min.
Oscillation stabilization time
MOST15
1
204.8 s min.
819.2 s min.
1.64 ms min.
3.27 ms min.
6.55 ms min.
f
X
= 10 MHz
MOST16
0
457
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