UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 231

• Manufacturer Part Number: UPD78F0535GB(T)-UEU-A
• Description: 8BIT MCU, 60K FLASH, 3KB RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0535GB(T)-UEU-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 60KB
• Oscillator Type: External, Internal

<R>
<1> Count operation start flow
(TOE0n, TOC0n4, TOC0n1)
Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control
Remarks 1. PPG pulse cycle = (M + 1) × Count clock cycle
Compare match interrupt
Compare match interrupt
Timer output control bits
TMC0n3, TMC0n2 bits = 11
CR00n, CR01n registers,
(TMC0n3, TMC0n2)
Register initial setting
register 0n (TOC0n).
TOC0n register
Compare register
Compare register
PRM0n register,
CRC0n register,
2. n = 0:
port setting
TM0n register
Operable bits
START
TO0n output
(INTTM00n)
(INTTM01n)
PPG duty = (N + 1)/(M + 1)
n = 0, 1:
Figure 7-47. Example of Software Processing for PPG Output Operation
(CR00n)
(CR01n)
0000H
Note
µ
µ
,
PD78F0531, 78F0532, 78F0533
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
00
<1>
Initial setting of these
registers is performed
before setting the
TMC0n3 and TMC0n2
bits.
Starts count operation
N + 1
M + 1
N
User’s Manual U17260EJ6V0UD
M
<2> Count operation stop flow
N + 1
11
TMC0n3, TMC0n2 bits = 00
M
N
M + 1
N
STOP
M
N + 1
M + 1
N
The counter is initialized
and counting is stopped
by clearing the TMC0n3
and TMC0n2 bits to 00.
M
<2>
00
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