UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 253
UPD78F0535GB(T)-UEU-A
Manufacturer Part Number
UPD78F0535GB(T)-UEU-A
Description
8BIT MCU, 60K FLASH, 3KB RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0535GB(T)-UEU-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
60KB
Oscillator Type
External, Internal
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(1) 8-bit timer counter 5n (TM5n)
(2) 8-bit timer compare register 5n (CR5n)
TM5n is an 8-bit register that counts the count pulses and is read-only.
The counter is incremented in synchronization with the rising edge of the count clock.
In the following situations, the count value is cleared to 00H.
<1> Reset signal generation
<2> When TCE5n is cleared
<3> When TM5n and CR5n match in the mode in which clear & start occurs upon a match of the TM5n and
CR5n can be read and written by an 8-bit memory manipulation instruction.
Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count
value, and an interrupt request (INTTM5n) is generated if they match.
In the PWM mode, TO5n output becomes inactive when the values of TM5n and CR5n match, but no interrupt is
generated.
The value of CR5n can be set within 00H to FFH.
Reset signal generation clears CR5n to 00H.
Cautions 1. In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 = 0), do
Remark n = 0, 1
CR5n.
2. In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock
Address: FF16H (TM50), FF1FH (TM51)
Address: FF17H (CR50), FF41H (CR51)
(n = 0, 1)
(n = 0, 1)
Symbol
Symbol
TM5n
CR5n
not write other values to CR5n during operation.
selected by TCL5n) or more.
Figure 8-4. Format of 8-Bit Timer Compare Register 5n (CR5n)
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Figure 8-3. Format of 8-Bit Timer Counter 5n (TM5n)
User’s Manual U17260EJ6V0UD
After reset: 00H
After reset: 00H
R
R/W
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