UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 305
UPD78F0535GB(T)-UEU-A
Manufacturer Part Number
UPD78F0535GB(T)-UEU-A
Description
8BIT MCU, 60K FLASH, 3KB RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0535GB(T)-UEU-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
60KB
Oscillator Type
External, Internal
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11.4.3 Setting window open period of watchdog timer
byte (0080H). The outline of the window is as follows.
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option
• If “ACH” is written to WDTE during the window open period, the watchdog timer is cleared and starts counting
• Even if “ACH” is written to WDTE during the window close period, an abnormality is detected and an internal
Example: If the window open period is 25%
Caution The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the
The window open period to be set is as follows.
Counting
starts
again.
reset signal is generated.
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0
overflow time regardless of the timing of the writing, and the watchdog timer starts counting
again.
WINDOW1
0
0
1
1
Internal reset signal is generated
if ACH is written to WDTE.
Window close period (75%)
2. The watchdog timer continues its operation during self-programming and EEPROM
Table 11-4. Setting Window Open Period of Watchdog Timer
is prohibited.
emulation of the flash memory. During processing, the interrupt acknowledge time
is delayed.
consideration.
WINDOW0
1
0
1
0
25%
50%
75%
100%
CHAPTER 11 WATCHDOG TIMER
Set the overflow time and window size taking this delay into
User’s Manual U17260EJ6V0UD
Window Open Period of Watchdog Timer
Counting starts again when
ACH is written to WDTE.
Window open
period (25%)
Overflow
time
305
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