UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 113
UPD78F9502MA-CAC-A
Manufacturer Part Number
UPD78F9502MA-CAC-A
Description
8BIT MCU, 4K FLASH, 128B RAM, SMD
Manufacturer
NEC
Datasheet
1.UPD78F9502MA-CAC-A.pdf
(229 pages)
Specifications of UPD78F9502MA-CAC-A
Controller Family/series
UPD78F
No. Of I/o's
8
Ram Memory Size
128Byte
Cpu Speed
10MHz
No. Of Timers
2
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
4KB
Oscillator Type
External, Internal
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(b) Release by reset signal generation
When the reset signal is input, STOP mode is released and a reset operation is performed after the
oscillation stabilization time has elapsed.
Note Operation is stopped (277 s (MIN.), 544 s (TYP.), 1.075 ms (MAX.)) because the option byte is
System clock
Reset signal
CPU status
oscillation
referenced.
Maskable interrupt request
Reset signal generation
: don’t care
Table 9-5. Operation in Response to Interrupt Request in STOP Mode
Release Source
Figure 9-5. STOP Mode Release by Reset signal generation
Operation
Oscillation
mode
instruction
STOP
Preliminary User’s Manual U18681EJ1V0UD
CHAPTER 9 STANDBY FUNCTION
STOP mode
MK
0
0
1
Oscillation stops.
IE
0
1
period
Reset
Next address instruction execution
Interrupt servicing execution
STOP mode held
Reset processing
Operation
stops
Operation
Note
.
Operation mode
Oscillation
113
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